Philips Semiconductors

Product specification

74F256

Dual addressable latch

2

1988 Nov 29

853–0359 95207

FEATURES

DESCRIPTION

The 74F256 dual addressable latch has four distinct modes of

operation which are selectable by controlling the Master Reset (MR)

and Enable (E) inputs (see Function Table). In the addressable latch

mode, data at the Data inputs is written into the addressed latches.

The addressed latches will follow the Data input with all

unaddressed latches remaining in their previous states. In the

memory mode, all latches remain in their previous states and are

unaffected by the Data or Address inputs. To eliminate the possibility

of entering erroneous data in the latches, the enable should be held

High (inactive) while the address lines are changing. In the dual

1-of-4 decoding or demultiplexing mode (MR=E=Low), addressed

outputs will follow the level of the Data inputs, with all other outputs

Low. In the Master Reset mode, all outputs are Low and unaffected

by the Address and Data inputs.

PIN CONFIGURATION

16

15

14

13

12

11

10

7

6

5

4

3

2

1

9

8

VCC

A0

A1

Da

Q0a

Q1a

Q2a

Q3a

GND

MR

E

Db

Q3b

Q2b

Q1b

Q0b

SF00805

TYPE

TYPICAL

PROPAGATION

DELAY

TYPICAL SUPPLY

CURRENT (TOTAL)

74F256

7.0ns

28mA

ORDERING INFORMATION

ORDER CODE

DESCRIPTION

COMMERCIAL RANGE

PKG DWG #

16-pin plastic DIP

N74F256N

SOT38-4

16-pin plastic SO

N74F256D

SOT109-1

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

PINS

DESCRIPTION

74F (U.L.)

HIGH/LOW

LOAD VALUE

HIGH/LOW

Da, Db

Port A, port B inputs

1.0/1.0

20

µA/0.6mA

A0, A1

Address inputs

1.0/1.0

20

µA/0.6mA

E

Enable (active Low)

1.0/1.0

20

µA/0.6mA

MR

Master Reset inputs (active Low)

1.0/1.0

20

µA/0.6mA

Q0a – Q3a

Port A outputs

50/33

1.0mA/20mA

Q0b – Q3b

Port B outputs

50/33

1.0mA/20mA

NOTE:

One (1.0) FAST unit load is defined as: 20

µA in the High state and 0.6mA in the Low state.