ADL6337ACRZA-R7 datasheet(4/41 Pages) AD

4 / 41 page

Data Sheet

ADL6337

SPECIFICATIONS

analog.com

Rev. B | 4 of 41

Table 2. Electrical Characteristics (Continued)

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

POWER SUPPLY

Voltage

4.75

5.0

5.25

Supply Current

High performance mode

460

Low power mode

380

400

Power-Down Current

DIGITAL LOGIC

Input Voltage

SCLK, SDIO, CS, CS_A2, CS_A1, CS_A0, TXENP

High (VIH)

1.07

Low (VIL)

0.68

Input Current

High (IIH)

−100

μA

Low (IIL)

100

μA

Output Voltage

SDO

At 1.8 V

High (VOH)

Output high current (IOH) = −100 μA or −1 mA static load

1.5

Low (VOL)

Output low current (IOL) = 100 μA or 1 mA static load

0.2

At 3.3 V

High (VOH)

IOH = −100 μA or −1 mA static load

2.7

Low (VOL)

IOL = 100 μA or 1 mA static load

0.2

DIGITAL LOGIC TIMING

Table 3. SPI AC Timing

Parameter

Description

Min

Typ

Max

Unit

fSCLK

Maximum serial clock rate, 1/tSCLK

MHz

tPWH

Minimum period that SCLK is in logic-high state

tPWL

Minimum period that SCLK is in logic-low state

tDS

Setup time between data and rising edge of SCLK

tDH

Hold time between data and rising edge of SCLK

tDCS

Setup time between falling edge of CS and rising edge of SCLK

Hold time between rising edge of CS and the last falling edge of SCLK, minimum 10ns

tDV

Maximum time delay between falling edge of SCLK and output data valid for a read operation

Maximum time delay between CS deactivation and SDIO bus return to high impedance

Timing Diagrams

Figure 2. SPI Register Timing, MSB First

ADL6337ACRZA-R7 Datasheet(PDF) 4 Page - Analog Devices

ADL6337ACRZA-R7 Datasheet(HTML) 4 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

Datasheet Descarga

Enlace URL