EM4006F9WS21 datasheet(7/10 Pages) EMMICRO

7 / 10 page

EM4006

 2001, EM Microelectronic-Marin SA

www.emmicroelectronic.com

Fig. 7

Miller Encoder

The input to Miller encoder is NRZ data coming from

LROM. The output is coded according to Miller format and

is driving the modulator Switch. See figure 6 for example

of Miller code.

Clock Generation

The clock of the logic is extracted from the RF signal. The

clock extracted from RF signal is driving the divider chain

consisting of toggle flip-flops. The output of this divider

chain is data clock with which the data from Laser ROM

(LROM) is addressed, encoded and sent to Modulator

Switch.

The layout of divider chain is designed in a way that

different data rates can be chosen with metal mask

(options).

The following division factors are possible on request:

128, 256, 1024, 2048, 4094 and 8192.

The standard is 512.

Others

As mentioned in Output Sequence, during the pause (LW)

the Modulator Switch is OFF. When observing the pause

duration one has to remember that the time with

Modulator Switch OFF effectively observed can vary due

to different terminations of STDMS. The stop bit at 0 can

be represented either by Modulator Switch ON or OFF

depending on the data. The start bit at 1 adds 1/2 of data

period OFF (transition in the middle of bit period).

Figure below show the four possible terminations of

STDMS and its influence on entire period passed by

Modulator Switch OFF. Level LOW represents Modulator

Switch OFF. LDB stands for last data bit.

time

modulator

ON/OFF

READ

64 bits

period

chip operating voltage range: from V

min to Vmax

max (voltage clipping)

min

r (Read wake up)

chip supply voltage

OFF

supply voltage

EM4006F9WS21 Datasheet(PDF) 7 Page - EM Microelectronic - MARIN SA

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