R

EM6607

Copyright © 2005, EM Microelectronic-Marin SA

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4

Reset

To initialize the EM6607, a system RESET must be executed. There are five methods of doing this:

(1)

Initial RESET from the oscillation detection circuit.

(2)

External RESET from the RESET PIN.

(3)

External RESET by simultaneous high input to terminals PA0..PA3.

(Combinations defined by metal option)

(4)

Watchdog RESET (software option).

(5)

Software Power-On-Reset by writing S0ftPOR bit in Option2 register to “1”

During any of these RESET’s the STB/RST output pin is high.

Figure 6.

System reset generation

4.1

Oscillation detection circuit

therefore counts the first 32768 oscillator clocks after power-on and holds the system in RESET. The system will consequently

remain in RESET for at least one second after power up.

After power up the Analogue Watchdog circuit monitors the oscillator. If it stops for any reason other then SLEEP mode, then a

RESET is generated and the STB/RST pin is driven high.

4.2

Reset Pin

During active or STANDBY mode the RESET terminal has a debouncer to reject noise and therefore must be active high for at

least 2ms or 16ms (CLK = 32kHz) - software selectable by DebCK in CIRQD register. (See Table 37)

When cancelling sleep mode, the debouncer is not active (no clock), however, reset passes through an analogue filter with a

time constant of typical. 5µs. In this case Reset pin must be high for at least 10 µs to generate a system reset.