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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

WED2ZLRSP01S

April, 2002

Rev. 0

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

CEx#

ADV

WE#

BWx#

OE#

CKE#

CK

Address Accessed

Operation

H

L

X

X

X

L

↑

N/A

Deselect

X

H

X

X

X

L

↑

N/A

Continue Deselect

L

L

H

X

L

L

↑

External Address

Begin Burst Read Cycle

X

H

X

X

L

L

↑

Next Address

Continue Burst Read Cycle

L

L

H

X

H

L

↑

External Address

NOP/Dummy Read

X

H

X

X

H

L

↑

Next Address

Dummy Read

L

L

L

L

X

L

↑

External Address

Begin Burst Write Cycle

X

H

X

L

X

L

↑

Next Address

Continue Burst Write Cycle

L

L

L

H

X

L

↑

N/A

NOP/Write Abort

X

H

X

H

X

L

↑

Next Address

Write Abort

X

X

X

X

X

H

↑

Current Address

Ignore Clock

TRUTH TABLES

SYNCHRONOUS TRUTH TABLE

WRITE TRUTH TABLE

WE#

BWa# BWb#

BWc# BWd#

Operation

H

X

X

X

X

Read

L

L

H

H

H

Write Byte a

L

H

L

H

H

Write Byte b

L

H

H

L

H

Write Byte c

L

H

H

H

L

Write Byte d

L

L

L

L

L

Write All Bytes

L

H

H

H

H

Write Abort/NOP

NOTES:

1. X means “Don’t Care.”

2. All inputs in this table must meet setup and hold time around the rising

edge of CK (

3. Applies to each of the independent arrays.

NOTES:

1. X means “Don’t Care.”

2. The rising edge of clock is symbolized by (

3. A continue deselect cycle can only be entered if a deselect cycle is executed first.

4. WRITE# = L means Write operation in WRITE TRUTH TABLE.

WRITE# = H means Read operation in WRITE TRUTH TABLE.

5. Operation finally depends on status of asynchronous input pins (ZZ and OE#).

7. Applies to each of the independent arrays.