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STM32F103CBU7TR Datasheet(PDF) 71 Page - STMicroelectronics |
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STM32F103CBU7TR Datasheet(HTML) 71 Page - STMicroelectronics |
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71 / 116 page ![]() DS5319 Rev 18 71/116 STM32F103x8, STM32F103xB Electrical characteristics 115 Figure 33. SPI timing diagram - slave mode and CPHA = 0 Figure 34. SPI timing diagram - slave mode and CPHA = 1(1) 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. (SI) MSB IN BIT1 IN LSB IN BIT6 OUT MSB OUT LSB OUT NSS input MOSI INPUT MISO OUTPUT (SI) ai14135b NSS input tSU(NSS) tc(SCK) th(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) ta(SO) tv(SO) th(SO) tr(SCK) tf(SCK) tdis(SO) MISO OUTPUT MOSI INPUT tsu(SI) th(SI) MSB OUT MSB IN BIT6 OUT LSB OUT LSB IN BIT 1 IN |
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