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C5NPARCH-RM/D Datasheet(PDF) 85 Page - NXP Semiconductors |
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C5NPARCH-RM/D Datasheet(HTML) 85 Page - NXP Semiconductors |
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85 / 114 page  AC Timing Specifications 85 03 Gigabit GMII Ethernet, TBI and MII Interface Timing Specifications The Gigabit GMII Ethernet interface timing is shown in Figure 16 and described in Table 44. The TBI interface timing is shown in Figure 16 and described in Table 45. Figure 16 Gigabit Ethernet and TBI Interface Timing Diagram Cycle 1 Cycle 2 Cycle 3 Tcmt Tcmo MII Tx Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Tcgt Tcgo GMII / TBI Tx Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Tctr Tctd Tcts Tcth TBI Rx MII CPn_1 (TCLKI) MII CPn_2-6 (Tx) Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 CPn+2_1 (RCLK) Tcgr Tcgs Tcgh GMII/MII Rx CPn+2_2-6 (Rx) CPn+3_1-6 (Rx) CPn_0 (TCLK) CPn_2-6 (Tx) CPn+1_2-6 (Tx) CPn+2_1 (RCLK) CPn+3_1 (RCLKN) CPn+2_2-6 (Rx) CPn+3_2-6 (Rx) Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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