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CSC05B Datasheet(PDF) 4 Page - Vishay Siliconix

No. de pieza CSC05B
Descripción Electrónicos  Thick Film Resistor Networks Single-In-Line, Coated SIP 01, 03, 05 Schematics
PDF  4 Pages
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Fabricante Electrónico  VISHAY [Vishay Siliconix]
Página de inicio  http://www.vishay.com
Logo VISHAY - Vishay Siliconix

CSC05B Datasheet(HTML) 4 Page - Vishay Siliconix

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35
CSC
Vishay Dale
Document Number: 31509
Revision 02-Aug-02
For Technical Questions, contact: ff2aresistors@vishay.com
TEST
Thermal Shock
Short Time Overload
Low Temperature Operation
Moisture Resistance
Resistance to Soldering Heat
Shock
Vibration
Load Life
Terminal Strength
Insulation Resistance
Dielectric Withstanding Voltage
MAX.
R (Typical Test Lots)
± 0.50% ∆R
± 0.25% ∆R
± 0.25% ∆R
± 1.00% ∆R
± 0.25% ∆R
± 0.25% ∆R
± 0.25% ∆R
± 1.00% ∆R
± 0.25% ∆R
PERFORMANCE
Thick Film Resistor Networks, Single-In-Line, Coated SIP
1
2
3
n-1
n
CIRCUIT APPLICATIONS
01 Schematic
Pulse squaring and TTL dual-line terminators
The CSCxxx-05 circuits contain series pairs of resistors. Each series pair is
connected between two common lines. The junction of these resistor pairs
is connected to the input terminals. The 05 circuits are designed for TTL dual-
line termination and pulse squaring.
* "B" Profile available. Odd pin available in 5, 7, 9 and 11.
"A" Profile = 2 through 6 isolated resistors
The CSCxxx-03 single-in-line resistor networks provide the user with nomi-
nally equal resistors. Each resistor is isolated from all others. Commonly
used in the following applications:
• "Wired OR" Pull-up
• Long-Line Impedance Balancing
• Power Driven Pull-up
• LED Current Limiting
• Power Gate Pull-up
• ECL Output Pull-down
• Line Termination
• TTL Input Pull-down
* "B" Profile available.
"A" Profile = 3, 5, 7, 9 and 11 resistors with one pin common
The CSCxxx-01 single-in-line resistor networks provide the user with nomi-
nally equal resistors, each connected to a common pin (Pin No. 1). Com-
monly used in the following applications:
• "Wired OR" Pull-up
• Open Collector Pull-up
• Power Gate Pull-up
• TTL Input Pull-down
• MOS/ROM Pull-up/Pull-down
• TTL Unused Gate Pull-up
* "B" Profile available. Odd pin available in 5, 7, 9, and 11.
1
2
3
n-1
n
1
2
3
4
n-1
n
03 Schematic
05 Schematic
R1
R2
CONDITIONS
5 cycles between - 65
°C and + 125°C
2.5 x rated working voltage, 5 seconds
45 minutes at full rated working voltage at - 65
°C
240 hours with humidity ranging from 80% RH to 98% RH
Leads immersed in + 350
°C solder to within 1/16" of body for 3 seconds
Total of 18 shocks at 100 G's
12 hours at maximum of 20 G's between 10 and 2,000 Hz
1,000 hours at + 70
°C, rated power applied 1.5 hours “ON”, 0.5 hour
“OFF” for full 1000 hour period. Derated according to the curve.
4.5 pound pull for 30 seconds
10,000 Megohm (minimum)
No evidence of arcing or damage (200 V RMS for 1 minute)



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