Nexperia

PIMD2

50 V, 100 mA NPN/PNP resistor-equipped double transistor; R1 = 22 kΩ, R2 = 22 kΩ

8. Limiting values

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

Per transistor

VCBO

collector-base voltage

open emitter

[1]

-

50

V

VCEO

collector-emitter voltage open base

[1]

-

50

V

VEBO

emitter-base voltage

open collector

[1]

-

10

V

TR1 (NPN)

-10

40

V

VI

input voltage

TR2 (PNP)

-40

10

V

IO

output current

[1]

-

100

mA

Ptot

total power dissipation

Tamb ≤ 25 °C

[2]

-

250

mW

Per device

Ptot

total power dissipation

Tamb ≤ 25 °C

[2]

-

400

mW

Tj

junction temperature

-

150

°C

Tamb

ambient temperature

-55

150

°C

Tstg

storage temperature

-65

150

°C

[1] For the PNP transistor with negative polarity.

[2] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided, 35 μm copper, tin-plated and standard footprint.

Tamb (°C)

-75

175

125

25

75

-25

aaa-036347

200

300

100

400

500

Ptot

(mW)

0

FR4 PCB, single-sided, 35 μm copper, tin-plated and standard footprint

Fig. 1. Per device: Power derating curve

PIMD2

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© Nexperia B.V. 2023. All rights reserved

Product data sheet

13 March 2023

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