 |
Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
|
Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
82P33731 Datasheet(PDF) 1 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
82P33731 Datasheet(HTML) 1 Page - Renesas Technology Corp |
|
|
1 / 66 page  1 ©2017 Integrated Device Technology, Inc. August 28, 2017 HIGHLIGHTS • Synchronous Equipment Timing Source (SETS) for Synchronous Ethernet (SyncE) per ITU-T G.8264 • DPLL1 generates ITU-T G.8262 compliant SyncE clocks, Telcordia GR-1244-CORE/GR-253-CORE, and ITU-T G.813 compliant SONET/ SDH clocks • DPLL2 performs rate conversions for synchronization interfaces or for other general purpose timing applications • APLL3 is Voltage Controlled Crystal Oscillator (VCXO) based and generates clocks with jitter <0.3 ps RMS (10 kHz to 20 MHz) for: 10GBASE-R, 10GBASE-W, 40GBASE-R and 100GBASE-R • APLL1 and APLL2 generate clocks with jitter < 1 ps RMS (12 kHz to 20 MHz) for: 1000BASE-T and 1000BASE-X • Fractional-N input dividers support a wide range of reference frequen- cies • Locks to 1 Pulse Per Second (PPS) references • DPLLs, APLL1 and APLL2 can be configured from an external EEPROM after reset FEATURES • Composite clock inputs (IN1 and IN2) accept 64 kHz synchronization interface signals per ITU-T G.703 • Differential reference inputs (IN3 to IN8) accept clock frequencies between 1 PPS and 650 MHz • Single ended inputs (IN9 to IN14) accept reference clock frequencies between 1 PPS and 162.5 MHz • Loss of Signal (LOS) pins (LOS0 to LOS3) can be assigned to any clock reference input • Reference monitors qualify/disqualify references depending on activ- ity, frequency and LOS pins • Automatic reference selection state machines select the active refer- ence for each DPLL based on the reference monitors, priority tables, revertive and non-revertive settings and other programmable settings • Fractional-N input dividers enable the DPLLs to lock to a wide range of reference clock frequencies including: 10/100/1000 Ethernet, 10G/ 40G/100G Ethernet, OTN, SONET/SDH, PDH, TDM, GSM, CPRI, and GNSS frequencies • Any reference inputs (IN3 to IN14) can be designated as external sync pulse inputs (1 PPS, 2 kHz, 4 kHz or 8 kHz) associated with a select- able reference clock input • FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS output sync pulses that are aligned with the selected external input sync pulse input and frequency locked to the associated reference clock input • DPLL1 can be configured with bandwidths between 0.09 mHz and 567 Hz • DPLL1 locks to input references with frequencies between 1 PPS and 650 MHz • DPLL2 locks to input references with frequencies between 8 kHz and 650 MHz • DPLL1 complies with ITU-T G.8262 for Synchronous Ethernet Equip- ment Clock (EEC), and G.813 for Synchronous Equipment Clock (SEC); and Telcordia GR-253-CORE/ GR-1244-CORE for Stratum 3 and SONET Minimum Clock (SMC) • DPLL1 generates clocks with PDH, TDM, GSM, CPRI/OBSAI, 10/100/ 1000 Ethernet and GNSS frequencies; these clocks are directly avail- able on OUT1 • DPLL2 generates N x 8 kHz clocks up to 100 MHz that are output on OUT9 and OUT10 • APLL1, APLL2 and APLL3 are connected to DPLL1 • APLL1 and APLL2 generate 10/100/1000 Ethernet, 10G Ethernet, or SONET/SDH frequencies • APLL3 generates 10G/40G/100G Ethernet, WAN-PHY, and LAN-PHY frequencies • Any of eight common TCXO/OCXO frequencies can be used for the System Clock: 10 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20 MHz, 24.576 MHz, 25 MHz, or 30.72 MHz • The I2C slave interface can be used by a host processor to access the control and status registers • The I2C master interface can automatically load a device configura- tion from an external EEPROM after reset; APLL3 must be configured via the I2C slave interface • DPLLs can be connected to an internal composite clock generator that outputs its 64 kHz synchronization signal on OUT8 • Differential outputs OUT3 to OUT6 output clocks with frequencies between 1 PPS and 650 MHz • Differential outputs OUT11 and OUT12 output clocks with frequencies up to 650 MHz • Single ended outputs OUT1, OUT2 and OUT7 output clocks with fre- quencies between 1 PPS and 125 MHz • Single ended outputs OUT9 and OUT10 output clocks N*8 kHz multi- ples up to 100 MHz • DPLL1 supports independent programmable delays for each of IN3 to IN14; the delay for each input is programmable in steps of 0.61 ns with a range of ~±78 ns • The input to output phase delay of DPLL1 is programmable in steps of 0.0745 ps with a total range of ±20 s • The clock phase of each of the output dividers for OUT1 (from APLL1) to OUT7 is individually programmable in steps of ~200 ps with a total range of +/-180° • 1149.1 JTAG Boundary Scan • 144-pin CABGA green package APPLICATIONS • Access routers, edge routers, core routers • Carrier Ethernet switches • Multi-service access platforms • PON OLT • LTE eNodeB • ITU-T G.8264 Synchronous Equipment Timing Source (SETS) • ITU-T G.8262 Synchronous Ethernet Equipment Clock (EEC) • ITU-T G.813 Synchronous Equipment Clock (SEC) • Telcordia GR-253-CORE/GR1244-CORE Stratum 3 Clock (S3) and SONET Minimum Clock (SMC) 82P33731 Datasheet Synchronous Equipment Timing Source for 10G/40G/100G Synchronous Ethernet |
Número de pieza similar - 82P33731 |
|
Descripción similar - 82P33731 |
|
|
Enlace URL |
| ¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Enlace a la hoja de datos | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Mexican ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
