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STM32U595AI Datasheet(PDF) 329 Page - STMicroelectronics

No. de pieza STM32U595AI
Descripción Electrónicos  Ultra-low-power Arm® Cortex®-M33 32-bit MCUTrustZone®FPU,240 DMIPS, up to 4 MB Flash, 2.5 MB SRAM, LTDC, MIPI® DSI
PDF  377 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
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STM32U595AI Datasheet(HTML) 329 Page - STMicroelectronics

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DS13633 Rev 1
329/377
STM32U59xxx
Electrical characteristics
343
5.3.36
HSPI characteristics
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature, fAHB frequency and VDD supply voltage
conditions summarized in Table 32, with the following configuration:
•
Output speed set to OSPEEDRy[1:0] = 11
•
Measurement points done at 0.5 × VDD level
•
I/O compensation cell activated
•
HSLV activated when VDD ≤ 2.7 V
•
Voltage scaling range 1 unless otherwise specified
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics.
5.3.37
SD/SDIO/e•MMC card host interfaces (SDMMC) characteristics
Unless otherwise specified, the parameters given in Table 140 and Table 141 are derived
from tests performed under the ambient temperature, fAHB frequency and VDD supply
voltage conditions summarized in Table 32, with the following configuration:
•
Output speed set to OSPEEDRy[1:0] = 10
•
Capacitive load CL = 30 pF, unless otherwise specified
•
Measurement points done at 0.5 × VDD level
•
I/O compensation cell activated
•
HSLV activated when VDD ≤ 2.7 V
•
Voltage scaling range 1
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output
characteristics.
Table 140. SD/e•MMC characteristics (VDD = 2.7 V to 3.6 V)(1)(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPP
Clock frequency in data transfer mode
-
0
-
100(3)
MHz
tW(CKL)
Clock low time
fPP = 52 MHz
8.5
9.5
-
ns
tW(CKH)
Clock high time
fPP = 52 MHz
8.5
9.5
-
CMD, D inputs (referenced to CK) in e•MMC legacy/SDR/DDR and SD HS/SDR(4)/DDR(4) modes
tISU
Input setup time HS
-
3.5
-
-
ns
tIH
Input hold time HS
-
1.5
-
-
tIDW(5)
Input valid window (variable window)
-
4.5
-
-
CMD, D outputs (referenced to CK) in e•MMC legacy/SDR/DDR and SD HS/SDR(4)/DDR(4) modes
tOV
Output valid time HS
-
-
6.5
7.5/8.5
(6)
ns
tOH
Output hold time HS
-
3
-
-



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