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STM32H7B3II Datasheet(PDF) 130 Page - STMicroelectronics

No. de pieza STM32H7B3II
Descripción Electrónicos  32-bit Arm® Cortex®-M7 280 MHz MCUs, 2-Mbyte flash memory, 1.4-Mbyte RAM, 46 com. and analog interfaces, SMPS, crypto
PDF  238 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32H7B3II Datasheet(HTML) 130 Page - STMicroelectronics

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Figure 39. Synchronous multiplexed NOR/PSRAM read timings
FMC_CLK
FMC_NEx
FMC_NADV
FMC_A[25:16]
FMC_NOE
FMC_AD[15:0]
AD[15:0]
D1
D2
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tw(CLK)
tw(CLK)
Data latency = 0
BUSTURN = 0
td(CLKL-NExL)
td(CLKH-NExH)
td(CLKL-NADVL)
td(CLKL-AV)
td(CLKL-NADVH)
td(CLKH-AIV)
td(CLKL-NOEL)
td(CLKH-NOEH)
td(CLKL-ADV)
td(CLKL-ADIV)
tsu(ADV-CLKH)
th(CLKH-ADV)
tsu(ADV-CLKH)
th(CLKH-ADV)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
Table 80. Synchronous multiplexed NOR/PSRAM read timings
Symbol
Parameter
Min(1)
Max(1)(2)
Unit
tw(CLK)
FMC_CLK period
2Tfmc_ker_ck –0.5
-
ns
td(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x=0..2)
-
2
td(CLKH_NExH)
FMC_CLK high to FMC_NEx high (x= 0…2)
Tfmc_ker_ck+1.5
-
td(CLKL-NADVL)
FMC_CLK low to FMC_NADV low
-
1
td(CLKL-NADVH)
FMC_CLK low to FMC_NADV high
0
-
td(CLKL-AV)
FMC_CLK low to FMC_Ax valid (x=16…25)
-
2.0
td(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid (x=16…25)
Tfmc_ker_ck+1.5
-
td(CLKL-NOEL)
FMC_CLK low to FMC_NOE low
-
1.5
td(CLKH-NOEH)
FMC_CLK high to FMC_NOE high
Tfmc_ker_ck +1.5
-
td(CLKL-ADV)
FMC_CLK low to FMC_AD[15:0] valid
-
3
td(CLKL-ADIV)
FMC_CLK low to FMC_AD[15:0] invalid
0
-
tsu(ADV-CLKH)
FMC_A/D[15:0] valid data before FMC_CLK high
3
-
STM32H7B3xI
Operating conditions
DS13139 - Rev 8
page 130/238



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