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STM32H7B3II Datasheet(PDF) 137 Page - STMicroelectronics

No. de pieza STM32H7B3II
Descripción Electrónicos  32-bit Arm® Cortex®-M7 280 MHz MCUs, 2-Mbyte flash memory, 1.4-Mbyte RAM, 46 com. and analog interfaces, SMPS, crypto
PDF  238 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32H7B3II Datasheet(HTML) 137 Page - STMicroelectronics

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Figure 46. NAND controller waveforms for common memory write access
tw(NWE)
th(NWE-D)
tv(NWE-D)
FMC_NWE
FMC_NOE
FMC_D[15:0]
td(D-NWE)
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NCEx
td(ALE-NOE)
th(NOE-ALE)
Table 84. Switching characteristics for NAND flash memory read cycles
Symbol
Parameter
Min(1)
Max(1)
Unit
tw(N0E)
FMC_NOE low width
4Tfmc_ker_ck – 0.5
4Tfmc_ker_ck+0.5
ns
tsu(D-NOE)
FMC_D[15-0] valid data before FMC_NOE high
8
-
th(NOE-D)
FMC_D[15-0] valid data after FMC_NOE high
0
-
td(ALE-NOE)
FMC_ALE valid before FMC_NOE low
-
3Tfmc_ker_ck +0.5
th(NOE-ALE)
FMC_NWE high to FMC_ALE invalid
4Tfmc_ker_ck –1
-
1. Guaranteed by characterization results.
Table 85. Switching characteristics for NAND flash write cycles
Symbol
Parameter
Min(1)
Max(1)
Unit
tw(NWE)
FMC_NWE low width
4Tfmc_ker_ck – 0.5
4Tfmc_ker_ck +0.5
ns
tv(NWE-D)
FMC_NWE low to FMC_D[15-0] valid
0
-
th(NWE-D)
FMC_NWE high to FMC_D[15-0] invalid
2Tfmc_ker_ck + 1.5
-
td(D-NWE)
FMC_D[15-0] valid before FMC_NWE high
5Tfmc_ker_ck – 2
-
td(ALE-NWE)
FMC_ALE valid before FMC_NWE low
-
3Tfmc_ker_ck +0.5
th(NWE-ALE)
FMC_NWE high to FMC_ALE invalid
2Tfmc_ker_ck + 0.5
-
1. Guaranteed by characterization results.
SDRAM waveforms and timings
In all timing tables, Tfmc_ker_ck is the kernel clock period, with the following FMC_SDCLK maximum values:
•
For 2.7 V < VDD <3.6 V: FMC_CLK =110 MHz at 20 pF
•
For 1.8 V < VDD <1.9 V: FMC_CLK =100 MHz at 20 pF
•
For 1.62 V <DD <1.8 V, FMC_CLK =100 MHz at 15 pF
STM32H7B3xI
Operating conditions
DS13139 - Rev 8
page 137/238



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