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STM32H7B3II Datasheet(PDF) 139 Page - STMicroelectronics

No. de pieza STM32H7B3II
Descripción Electrónicos  32-bit Arm® Cortex®-M7 280 MHz MCUs, 2-Mbyte flash memory, 1.4-Mbyte RAM, 46 com. and analog interfaces, SMPS, crypto
PDF  238 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32H7B3II Datasheet(HTML) 139 Page - STMicroelectronics

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Table 87. LPSDR SDRAM read timings
Symbol
Parameter
Min(1)
Max(1)(2)
Unit
tW(SDCLK)
FMC_SDCLK period
2Tfmc_ker_ck – 1
2Tfmc_ker_ck+0.5
ns
tsu(SDCLKH_Data)
Data input setup time
3
-
th(SDCLKH_Data)
Data input hold time
0.5
-
td(SDCLKL_Add)
Address valid time
-
3.5
td(SDCLKL_SDNE)
Chip select valid time
-
2.5(3)
th(SDCLKL_SDNE)
Chip select hold time
0
-
td(SDCLKL_SDNRAS
SDNRAS valid time
-
1
th(SDCLKL_SDNRAS)
SDNRAS hold time
0
-
td(SDCLKL_SDNCAS)
SDNCAS valid time
-
1.5
th(SDCLKL_SDNCAS)
SDNCAS hold time
0
-
1. Guaranteed by characterization results.
2. At VOS1, these values are degraded by up to 5 %.
3. Using PC2_C I/O adds 16.5 ns to this timing.
Figure 48. SDRAM write access waveforms
Row n
Col1
FMC_SDCLK
FMC_A[12:0]
FMC_SDNRAS
FMC_SDNCAS
FMC_SDNWE
FMC_D[31:0]
FMC_SDNE[1:0]
td(SDCLKL_AddR)
td(SDCLKL_AddC)
th(SDCLKL_AddR)
th(SDCLKL_AddC)
td(SDCLKL_SNDE)
td(SDCLKL_Data)
th(SDCLKL_Data)
Col2
Coli
Coln
Data2
Datai
Datan
Data1
th(SDCLKL_SNDE)
td(SDCLKL_NRAS)
td(SDCLKL_NCAS)
th(SDCLKL_NCAS)
th(SDCLKL_NRAS)
td(SDCLKL_NWE)
th(SDCLKL_NWE)
FMC_NBL[3:0]
td(SDCLKL_NBL)
STM32H7B3xI
Operating conditions
DS13139 - Rev 8
page 139/238



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