STM32H7B3II datasheet(144/238 Pages) STMICROELECTRONICS

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Figure 53. OctoSPI Hyperbus write

NCS

Access latency

Latency count

Command address

47:40 39:32 31:24 23:16

15:8

7:0

Dn+1

Host drives DQ[7:0] and the memory drives RWDS.

Host drives DQ[7:0] and RWDS.

CLK, NCLK

RWDS

DQ[7:0]

tw(CS)

tv(RWDS)

tv(CLK)

th(CLK)

High = 2x latency count

Low = 1x latency count

Read write recovery

th(OUT)

tv(OUT)

th(OUT)

tv(OUT)

th(OUT)

tv(OUT)

6.3.20

Delay block (DLYB) characteristics

Unless otherwise specified, the parameters given in Table 92. Delay Block characteristics for Delay Block are

derived from tests performed under the ambient temperature, frcc_cpu_ck frequency and VDD supply voltage

summarized in Table 22. General operating conditions, with the following configuration:

Table 92. Delay Block characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

tinit

Initial delay

1400

1700

2700

t∆

Unit Delay

6.3.21

16-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 93. ADC characteristics are derived from tests

performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized

in Table 22. General operating conditions.

Table 93. ADC characteristics

Symbol

Parameter

Conditions

Min(1)

Typ(1)

Max(1)

Unit

VDDA

Analog power supply

for ADC ON

1.62

3.6

VREF+(2)

Positive reference

voltage

VDDA ≥ 2 V

1.62

VDDA

VDDA < 2 V

VDDA

VREF-(2)

Negative reference

voltage

VSSA

fADC

ADC clock frequency

1,62 V ≤VDDA ≤ 3.6 V

BOOST =

0.12

MHz

BOOST =

0.12

BOOST =

0.12

12.5

BOOST =

6.25

STM32H7B3xI

Operating conditions

DS13139 - Rev 8

page 144/238

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