STM32H7B3II datasheet(142/238 Pages) STMICROELECTRONICS

No. de pieza	STM32H7B3II

Descripción Electrónicos	32-bit Arm® Cortex®-M7 280 MHz MCUs, 2-Mbyte flash memory, 1.4-Mbyte RAM, 46 com. and analog interfaces, SMPS, crypto

PDF	238 Pages

Scroll/Zoom	100%

Fabricante Electrónico	STMICROELECTRONICS [STMicroelectronics]

Página de inicio	http://www.st.com

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Figure 49. OctoSPI timing diagram - SDR mode

Data output

Clock

Data input

t(CLK)

tw(CLKH)

tw(CLKL)

tr(CLK)

tf(CLK)

ts(IN)

th(IN)

tv(OUT)

th(OUT)

Table 91. OCTOSPI characteristics in DTR mode (with DQS)/Octal and Hyperbus

Symbol

Parameter

Conditions

Min(1)

Typ(1)

Max(1)(2)

Unit

F(CLK)(3)(4)

OCTOSPI clock

frequency

1.71 V < VDD < 3.6 V, VOS0,

CLOAD = 15 pF

120(5)

MHz

2.7 V < VDD < 3.6 V, VOS0,

CLOAD = 20 pF

100

1.62 V < VDD < 2.5 V, VOS0,

CLOAD = 20 pF

100/45(6)

tw(CLKH)

OCTOSPI clock high

and low time

PRESCALER[7:0] = n = 0,1,3,5

t(CLK)/2

t(CLK)/2+1

tw(CLKL)

t(CLK)/2−1

t(CLK)/2

tw(CLKH)

OCTOSPI clock high

and low time

PRESCALER[7:0] = n = 2,4,6,8

(n/2)*t(CLK)/

(n+1)

(n/2)*t(CLK)/

(n+1)+1

tw(CLKL)

(n/2+1)*t(CLK)/

(n+1)−1

(n/2+1)*t(CLK)/

(n+1)

tv(CLK)

Clock valid time

t(CLK)+1

th(CLK)

Clock hold time

t(CLK)/2−0.5

t(CLK)/2

tw(CS)

Chip select high time

3 x t(CLK)

tv(DQ)

Data input vallid time

tv(DS)

Data strobe input

valid time

th(DS)

Data strobe input hold

time

tv(RWDS)

Data strobe output

valid time

3 x t(CLK)

tsr(DQ)

tsf(DQ)(7)

Data input setup time

−1

thr(DQ)

Data input hold time

Rising edge

thf(DQ)(7)

Falling edge

3.5

tvr(OUT)

tvf(OUT)

Data output valid time

DHQC = 0

5.5

7(8)

DHQC = 1, PRESCALER[7:0]=1,2...

t(CLK)/4+

t(CLK)/4+2(8)

thr(OUT)

thf(OUT)

Data output hold time

DHQC = 0

4.5

STM32H7B3xI

Operating conditions

DS13139 - Rev 8

page 142/238

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