BLUENRG-332VC datasheet(6/67 Pages) STMICROELECTRONICS

No. de pieza	BLUENRG-332VC

Descripción Electrónicos	Programmable Bluetooth® Low Energy wireless SoC

PDF	67 Pages

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Fabricante Electrónico	STMICROELECTRONICS [STMicroelectronics]

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Functional overview

2.1

System architecture

The main system consists of 32-bit multilayer AHB bus matrix that interconnects:

•

Three masters:

–

CPU (Cortex-M0+) core S-bus

–

DMA1

–

Radio system

•

Seven slaves:

–

Internal flash memory on CPU (Cortex-M0+) S bus

–

Internal SRAM0 (12 Kbytes)

–

Internal SRAM1 (12 Kbytes)

–

APB0 peripherals (through an AHB to APB bridge)

–

APB1 peripherals (through an AHB to APB bridge)

–

AHB0 peripherals

–

AHBRF including AHB to APB bridge and radio peripherals (connected to APB2)

The bus matrix provides access from a master to a slave, enabling concurrent access and efficient operation even

when several high-speed peripherals work simultaneously.

Figure 2. Bus matrix

CPU ARM

Cortex-M0+

SRAM1

Flash

Controller

Radio

system

APB1

DMA 1

APB0

AHB0

APB2

SRAM0

Bus matrix

BlueNRG-LPS

Functional overview

DS13819 - Rev 4

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