Parameter

Symbol

Min.

Typ.

Max.

Units

Test conditions

DYNAMIC CHARACTERISTICS

Signal-to-noise ratio

SNR

86

dB

VIN+=-200 mV to +200 mV

fMCLKIN = 5 to 15 MHz

VIN+=-250 mV to +250 mV

fMCLKIN = 20 MHz

Signal-to-(noise + distortion) ratio

SNDR

80

dB

Effective number of bits

ENOB

13

bits

Spurious free dynamic Range

SFDR

83

dB

Total harmonic distortion

THD

-83

dB

Common-mode transient immunity(1)

CMTI

25

30

kV/µs

Transient Pulse repetition frequency

up to 100 KHz

POWER SUPPLY

VDDISO supply current

IDDISO

35

mA

@ 25 MHz

30

mA

@ 10 MHz

VDD supply current

IDD

13

mA

VDD = 5 V,

fMCLKIN = 25 MHz

11

mA

VDD = 5 V,

fMCLKIN = 10 MHz

12.5

mA

VDD = 3.3 V,

fMCLKIN = 25 MHz

10.5

mA

VDD = 3.3 V,

fMCLKIN = 10 MHz

1. Guaranteed by characterization

Table 9. Timing specifications

Parameter

Symbo

l

Min.

Typ.

Max.

Units

Test conditions

Modulator clock input frequency

fCK

5

25

MHz

Clock duty cycle 48% to 52%

Data delay after rising edge of CK

tD

5

20

ns

CL = 15 pF

Figure 4. Timing sequence diagram

MCLK

MDAT

tD

MCLK period

1

2

3

4

The data is provided to the MDAT output 2 clock cycles after the effective sampling instant.

ISOSD61

Device specifications

DS13605 - Rev 8

page 7/23