5

Theory of operation

The differential analog input of the ISOSD61 implements a second-order modulator stage that digitizes the input

signal into a 1-bit output stream. The sample clock (MCLKIN) provided externally, is the clock signal for the

conversion process as well as the output data-framing clock. The analog input signal is continuously sampled

by the modulator and compared to an internal voltage reference. A digital stream that accurately represents the

analog input over time appears at the output of the converter.

Figure 5. Sigma-Delta data stream vs. differential input voltage ramp

SD output

Input

A differential signal of 0 V results (ideally) in a stream of alternating 1s and 0s at the MDAT output pin. This output

is high 50% of the time and low 50% of the time. Any differential input voltage produces a stream whose ratio

between 1s and the total number of pulses of the time is proportional to the ratio between the input voltage and

the full-scale differential range (+320 mV - -320 mV= 640 mV). The correspondent equation is:

nr of 1s

tot nr of pulses=0.5+Vin640

Where: Vin: input differential voltage [mV]; nr of 1s: count of 1 bit over a given time; tot nr of pulses: count of the

total 1 and 0 bits over the given time.

This means for a maximum positive differential input signal +320 mV there would be only 1s (signal stuck at 1)

and for a maximum negative of -320 mV only 0s (signal stuck at 0).

To decode the original information, the digital output stream must be digitally filtered and decimated. A

recommended filter is the SINC3 3rd order decimator. The SINC3 filter can be easily realized, for instance, with a

FPGA or an MCU like STM32.

5.1

Analog inputs

The analog front-end of the modulator implements a differential switched capacitor circuitry, whose purpose is

to sample and hold the analog signal every clock cycle. Like any A/D converter, to prevent the conversion of

aliasing signal, in accordance to the Nyquist-Shannon theorem, a low-pass filter should be added at the analog

inputs. Its cut- frequency should be below half the sampling frequency. The capacitors of this LP filter help to

smooth the undershoots and overshoots of the internal switching capacitors. Every switching has a charge current

injected, and the effective impedance of the analog inputs decreases with the clock frequency increasing. To

avoid undesired signal voltage drops, the LP filter resistors should have a value in the order of tenth of ohms.

5.2

Digital filtering

A typical filtering technique for sigma-delta modulators is the implementation af an SINC3 digital filter. The code

below is an example of a generic SINC3 filter written for GNU Octave that can be easily ported to other languages

or systems:

function [output, output_dec]=sinc3_generic(in)

ISOSD61

Theory of operation

DS13605 - Rev 8

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