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STUW81300 Datasheet(PDF) 34 Page - STMicroelectronics |
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STUW81300 Datasheet(HTML) 34 Page - STMicroelectronics |
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34 / 63 page  Circuit description STuW81300 34/63 DS11314 Rev 7 The Data bits are stored in the internal shift register on the rising edge of SCK. The first bit, CO is used for mode selection (0=Write Operation, 1=Read Operation). The bits A[3:0] represent the register address, and D[26:0] are the data bits. In some registers, the first data bit, D26, is used (when set to ‘1’) for double-buffering purposes. In this case the register content is stored in a temporary buffer and is transferred to the internal register once a write operation is done on the master register ST0. Figure 25. SPI timing diagram MsV43275V1 Tsetup Thold SDI LD_SDO SCK LE MSB MSB - 1 LSB Tcd Tdi Tck Tec Table 9. SPI timings Parameter Comments Min Typ Max Unit Tsetup Data to clock setup time 4- - ns Thold Data to clock hold time 1- - ns Tck Clock cycle period 20 - - ns Tdi Disable pulse width 4- - ns Tcd Clock-to-disable time 1- - ns Tec Enable-to-clock time 3- - ns |
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