EL5481, EL5482

FN7199 Rev 0.00

Page 8 of 9

June 14, 2001

Applications Information

Power Supplies and Circuit Layout

The EL5481 and EL5482 comparators operate with single and

dual supply with 5V to 12V between VS+ and VS-. The output

side of the comparators is supplied by a single supply from

2.7V to 5V. The rail to rail output swing enables direct

connection of the comparator to both CMOS and TTL logic

circuits. As with many high speed devices, the supplies must

be well bypassed. Elantec recommends a 4.7µF tantalum in

parallel with a 0.1µF ceramic. These should be placed as close

as possible to the supply pins. Keep all leads short to reduce

stray capacitance and lead inductance. This will also minimize

unwanted parasitic feedback around the comparator. The

device should be soldered directly to the PC board instead of

using a socket. Use a PC board with a good, unbroken low

inductance ground plane. Good ground plane construction

techniques enhance stability of the comparators.

Input Voltage Considerations

The EL5481 and EL5482 input range is specified from 0.1V

below VS- to 2.25V below VS+. The criterion for the input limit

is that the output still responds correctly to a small differential

input signal. The differential input stage is a pair of PNP

transistors, therefore, the input bias current flows out of the

device. When either input signal falls below the negative input

voltage limit, the parasitic PN junction formed by the substrate

and the base of the PNP will turn on, resulting in a significant

increase of input bias current. If one of the inputs goes above

the positive input voltage limit, the output will still maintain the

correct logic level as long as the other input stays within the

input range. However, the propagation delay will increase.

When both inputs are outside the input voltage range, the

output becomes unpredictable. Large differential voltages

greater than the supply voltage should be avoided to prevent

damages to the input stage. Inputs of unused channels should

not be left floating. They should be driven to a known state. For

example, one input can be tied to ground and the other input

can be connected to some voltage reference (like ±100mV) to

avoid oscillation in the output due to unwanted output to input

feedback.

Input Slew Rate

Most high speed comparators oscillate when the voltage of

one of the inputs is close to or equal to the voltage on the other

input due to noise or undesirable feedback. For clean output

waveform, the input must meet certain minimum slew rate

requirements. In some applications, it may be helpful to apply

some positive feedback (hysteresis) between the output and

the positive input. The hysteresis effectively causes one

comparator's input voltage to move quickly past the other, thus

taking the input out of the region where oscillation occurs. For

the EL5481 and EL5482, the propagation delay increases

when the input slew rate increases for low overdrive voltages.

With high overdrive voltages, the propagation delay does not

change much with the input slew rate.

Latch Pin Dynamics

The EL5482 contains a “transparent” latch for each channel.

The latch pin is designed to be driven with either a TTL or

CMOS output. When the latch is connected to a logic high level

or left floating, the comparator is transparent and immediately

responds to the changes at the input terminals. When the latch

is switched to a logic low level, the comparator output remains

latched to its value just before the latch’s high-to-low transition.

To guarantee data retention, the input signal must remain the

same state at least 1ns (hold time) after the latch goes low and

at least 2ns (setup time) before the latch goes low. When the

latch goes high, the new data will appear at the output in

approximately 6ns (latch propagation delay). The EL5481 has

no latch pins.

Hysteresis

Hysteresis can be added externally. The following two

methods can be used to add hysteresis.

Inverting comparator with hysteresis:

R3 adds a portion of the output to the threshold set by R1 and

R2. The calculation of the resistor values are as follows:

Select the threshold voltage VTH and calculate R1 and R2. The

current through R1/R2 bias string must be many times greater

than the input bias current of the comparator:

Let the hysteresis be VH, and calculate R3:

where:

VO=VSD-0.8V (swing of the output)

Recalculate R2 to maintain the same value of VTH:

Non inverting comparator with hysteresis:

R3 adds a portion of the output to the positive input. Note that

the current through R3 should be much greater than the input

bias current in order to minimize errors. The calculation of the

resistor values as follows:

+

-

R3

VIN

VREF

R2

R1

VTH

VREF

R1

R1 R2

+

---------------------



=

R3

VO

VH

--------

R1



R2





=

R21VREF



VTH

VTH

R1

-----------









–

VTH 0.5VSD

–

R3

--------------------------------------







+

=

+

-

R3

VIN

VREF

R1