DSPIC30F datasheet(73/248 Pages) MICROCHIP

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 2004 Microchip Technology Inc.

Preliminary

DS70083G-page 71

dsPIC30F

7.3

Writing to the Data EEPROM

To write an EEPROM data location, the following

sequence must be followed:

Erase data EEPROM word.

Select word, data EEPROM erase, and set

WREN bit in NVMCON register.

Write address of word to be erased into

NVMADR.

Enable NVM interrupt (optional).

Write ‘55’ to NVMKEY.

Write ‘AA’ to NVMKEY.

Set the WR bit. This will begin erase cycle.

Either poll NVMIF bit or wait for NVMIF

interrupt.

The WR bit is cleared when the erase cycle

ends.

Write data word into data EEPROM write

latches.

Program 1 data word into data EEPROM.

Select word, data EEPROM program, and

set WREN bit in NVMCON register.

Enable NVM write done interrupt (optional).

Write ‘55’ to NVMKEY.

Write ‘AA’ to NVMKEY.

Set the WR bit. This will begin program

cycle.

Either poll NVMIF bit or wait for NVM

interrupt.

The WR bit is cleared when the write cycle

ends.

The write will not initiate if the above sequence is not

exactly followed (write 0x55 to NVMKEY, write

0xAA to

NVMCON, then set WR bit) for each word. It is strongly

recommended that interrupts be disabled during this

code segment.

Additionally, the WREN bit in NVMCON must be set to

enable writes. This mechanism prevents accidental

writes to data EEPROM due to unexpected code exe-

cution. The WREN bit should be kept clear at all times

except when updating the EEPROM. The WREN bit is

not cleared by hardware.

After a write sequence has been initiated, clearing the

WREN bit will not affect the current write cycle. The WR

bit will be inhibited from being set unless the WREN bit

is set. The WREN bit must be set on a previous instruc-

tion. Both WR and WREN cannot be set with the same

instruction.

At the completion of the write cycle, the WR bit is

cleared in hardware and the Non-Volatile Memory

Write Complete Interrupt Flag bit (NVMIF) is set. The

user may either enable this interrupt or poll this bit.

NVMIF must be cleared by software.

7.3.1

WRITING A WORD OF DATA

EEPROM

Once the user has erased the word to be programmed,

then a table write instruction is used to write one write

latch, as shown in Example 7-4.

EXAMPLE 7-4:

DATA EEPROM WORD WRITE

; Point to data memory

MOV

#LOW_ADDR_WORD,W0

; Init pointer

MOV

#HIGH_ADDR_WORD,W1

MOV

W1,TBLPAG

MOV

#LOW(WORD),W2

; Get data

TBLWTL

W2,[ W0]

; Write data

; The NVMADR captures last table access address

; Select data EEPROM for 1 word op

MOV

#0x4004,W0

MOV

W0,NVMCON

; Operate key to allow write operation

DISI

; Block all interrupts with priority <7 for

; next 5 instructions

MOV

#0x55,W0

MOV

W0,NVMKEY

; Write the 0x55 key

MOV

#0xAA,W1

MOV

W1,NVMKEY

; Write the 0xAA key

BSET

NVMCON,#WR

; Initiate program sequence

NOP

; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle

; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete

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