ICS843156AKI REVISION B NOVEMBER 28, 2012

2

©2012 Integrated Device Technology, Inc.

ICS843156I Data Sheet

CRYSTAL-TO-LVPECL CLOCK SYNTHESIZER

Table 1. Pin Descriptions

NOTE: Pulldown refers to an internal input resistor. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Function Table

Table 3. Bypass Function Table

Number

Name

Type

Description

1,

2

XTAL_IN

XTAL_OUT

Input

Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.

3, 32

VCC

Power

Core supply pins.

4, 5

nQC1, QC1

Output

Differential output pair. LVPECL interface levels.

6, 7

nQC0, QC0

Output

Differential output pair. LVPECL interface levels.

8, 16, 25

VCCO

Power

Output supply pins.

9, 10

nQB1, QB1

Output

Differential output pair. LVPECL interface levels.

11, 12

nQB0, QB0

Output

Differential output pair. LVPECL interface levels.

13, 30

VEE

Power

Negative supply pins.

14, 15

nQA5, QA5

Output

Differential output pair. LVPECL interface levels.

17, 18

nQA4, QA4

Output

Differential output pair. LVPECL interface levels.

19, 20

nQA3, QA3

Output

Differential output pair. LVPECL interface levels.

21, 22

nQA2, QA2

Output

Differential output pair. LVPECL interface levels.

23, 24

nQA1, QA1

Output

Differential output pair. LVPECL interface levels.

26, 27

nQA0, QA0

Output

Differential output pair. LVPECL interface levels.

28

VCCA

Power

Analog supply pin.

29

BYPASS

Input

Pulldown

A HIGH on BYPASS signal allows TEST_CLK to propagate to output

dividers and bypass the PLL. a LOW on BYPASS signal allows VCO

frequency to propagate to the output dividers. See Table 3.

LVCMOS/LVTTL interface levels.

31

TEST_CLK

Input

Pulldown

Single-ended input test clock. LVCMOS interface levels.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

CIN

Input Capacitance

4

pF

RPULLDOWN

Input Pulldown Resistor

51

k



Input

Device Configuration

BYPASS

0PLL Mode

1

Bypass the PLL