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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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APR15/D Datasheet(PDF) 83 Page - NXP Semiconductors |
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APR15/D Datasheet(HTML) 83 Page - NXP Semiconductors |
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83 / 101 page  DSP56001A Host Port Considerations MOTOROLA DSP56001A/D, Rev. 1 4-9 DSP Programming Considerations SYNCHRONIZATION OF STATUS BITS FROM HOST TO DSP DMA, HF1, HF0, and HCP, HTDE, and HRDF status bits are set or cleared by the host processor side of the interface. These bits are individually synchronized to the DSP clock. (Refer to the User’s Manual for descriptions of these status bits.) READING HF0 AND HF1 AS AN ENCODED PAIR Care must be exercised when reading status bits HF0 and HF1 as an encoded pair, because the four combinations (00, 01, 10, and 11) each have significance. A very small probability exists that the DSP will read the status bits during transition. Therefore, HF0 and HF1 should be read twice and checked for consensus. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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