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PowerPC 604 RISC Microprocessor Technical Summary

and double-precision). For 64-bit PowerPC implementations, the PowerPC architecture provides additional

64-bit integer data types, 64-bit addressing, and related features.

The 604 is a superscalar processor capable of issuing four instructions simultaneously. As many as six

instructions can finish execution in parallel. The 604 has six execution units that can operate in parallel:

•

Floating-point unit (FPU)

•

Branch processing unit (BPU)

•

Load/store unit (LSU)

•

Three integer units (IUs):

— Two single-cycle integer units (SCIUs)

— One multiple-cycle integer unit (MCIU)

This parallel design, combined with the PowerPC architecture’s specification of uniform instructions that

allows for rapid execution times, yields high efficiency and throughput. The 604’s rename buffers,

reservation stations, dynamic branch prediction, and completion unit increase instruction throughput,

guarantee in-order completion, and ensure a precise exception model. (Note that the PowerPC architecture

specification refers to all exceptions as interrupts.)

The 604 has separate memory management units (MMUs) and separate 16-Kbyte on-chip caches for

instructions and data. The 604 implements two 128-entry, two-way set (64-entry per set) associative

translation lookaside buffers (TLBs), one for instructions and one for data, and provides support for

demand-paged virtual memory address translation and variable-sized block translation. The TLBs and the

cache use least-recently used (LRU) replacement algorithms.

The 604 has a 64-bit external data bus and a 32-bit address bus. The 604 interface protocol allows multiple

masters to compete for system resources through a central external arbiter. Additionally, on-chip snooping

logic maintains data cache coherency for multiprocessor applications. The 604 supports single-beat and

burst data transfers for memory accesses and memory-mapped I/O accesses.

The 604 uses an advanced, 3.3-V CMOS process technology and is fully compatible with TTL devices.

1.1.1 PowerPC 604 Microprocessor Features

This section summarizes features of the 604’s implementation of the PowerPC architecture.

Figure 1 provides a block diagram showing features of the 604. Note that this is a conceptual block diagram

intended to show the basic features rather than an attempt to show how these features are physically

implemented on the chip.

Freescale Semiconductor, Inc.

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