AD7021 datasheet(21/44 Pages) AD

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Preliminary Technical Data

ADF7021

Rev. PrI | Page 21 of 44

LINEAR 2FSK DEMODULATOR

Figure 22 shows a block diagram of the linear 2FSK

demodulator.

SLICER

FREQUENCY

LEVEL

LIMITER

LINEAR DISCRIMINATOR

R4_DB(20:29)

FREQUENCY

READBACK

AND

AFC LOOP

RxDATA

Figure 22. Block Diagram of Frequency Measurement System and

Linear FSK Demodulator

This method of frequency demodulation is useful when the

system protocol cannot support the overhead of the settling

time of the internal feedback AFC loop.

A digital frequency discriminator provides an output signal that

is linearly proportional to the frequency of the limiter outputs.

The discriminator output is then filtered and averaged using a

combined averaging filter and envelope detector. The demodu-

lated 2FSK data is recovered by threshold detecting the output

of the averaging filter, as shown in Figure 22. In this mode, the

slicer output shown in Figure 22 is routed to the data synchro-

nizer PLL for clock synchronization. To enable the linear FSK

demodulator, set Bits R4_DB[4:6] to 000.

The 3 dB bandwidth of the postdemodulation filter is set in the

same way as the 2FSK correlator/demodulator, which is set in

R4_DB[20:29] and is defined as

CLK

DEMOD

Setting

Demod

Post

CUTOFF

where:

FCUTOFF is the target 3 dB bandwidth in Hz of the

postdemodulator filter.

DEMOD_CLK is as defined in the Register 3—

Transmit/Receive Clock Register Comments section.

3FSK DEMODULATOR

The 3FSK demodulator uses a pair of digital frequency

correlators followed by a Viterbi decoder and clock and data

recovery to perform three-level FSK demodulation. To enable

3FSK demodulation, Bits R4_DB[4:6] must be set to 010. The

settings for the 3FSK demodulator are set in Register 13. The

post demod BW, discriminator BW, dot product, and Rx invert

settings of Register 4 also need to be set appropriately as

outlined in the FSK Correlator/Demodulator section.

4FSK DEMODULATOR

The 4FSK demodulator uses a pair of digital frequency

correlators and clock and data recovery to perform four-level

FSK demodulation. To enable 4FSK demodulation, Bits

R4_DB[4:6] must be set to 011. The post demod BW,

discriminator BW, dot product, and Rx invert settings of

FSK Correlator/Demodulator section.

AFC SECTION

The ADF7021 supports a real-time AFC loop that is used to

remove frequency errors that can arise due to mismatches between

the transmit and receive crystals. The AFC loop also uses the

frequency discriminator block, as described in the Linear 2FSK

Demodulator section and in Figure 22. The discriminator output

is filtered and averaged to remove the FSK frequency

modulation using a combined averaging filter and envelope

detector. In receive mode, the output of the envelope detector

provides an estimate of the average IF frequency.

Two methods of AFC, external and internal, are supported on

the ADF7021.

External AFC

Here, the user reads back the frequency information through

the ADF7021 serial port and applies a frequency correction

value to the fractional-N synthesizer N divider.

The frequency information is obtained by reading the 16-bit

signed AFC_readback, as described in the Readback Format

section, and by applying the following formula:

FREQ_RB [Hz] = (AFC_READBACK × DEMOD_CLK)/218

Note that while the AFC_READBACK value is a signed

number, under normal operating conditions it is positive. In the

absence of frequency errors, the FREQ_RB value is equal to the

IF frequency of 100 kHz.

AD7021 Datasheet(PDF) 21 Page - Analog Devices

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