AD9397SLASHPCB datasheet(5/28 Pages) AD

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AD9397

Rev. 0 | Page 5 of 28

Test

AD9397KSTZ-100

AD9397KSTZ-150

Parameter

Level

Conditions

Min

Typ

Max

Min

Typ

Max

Unit

AC SPECIFICATIONS

Intrapair (+ to −) Differential Input Skew

(TDPS)

360

Channel to Channel Differential Input

Skew (TCCS)

Clock

Period

Low-to-High Transition Time for Data

and Controls (DLHT)

Output drive = high;

CL = 10 pF

900

Output drive = low;

CL = 5 pF

1300

Low-to-High Transition Time for DATACK

(DLHT)

Output drive = high;

CL = 10 pF

650

Output drive = low;

CL = 5 pF

1200

High-to-Low Transition Time for Data

and Controls (DHLT)

Output drive = high;

CL = 10 pF

850

Output drive = low;

CL = 5 pF

1250

High-to-Low Transition Time for DATACK

(DHLT)

Output drive = high;

CL = 10 pF

800

Output drive = low;

CL = 5 pF

1200

Clock to Data Skew5 (TSKEW)

−0.5

+2.0

−0.5

+2.0

Duty Cycle, DATACK5

DATACK Frequency (FCIP)

150

MHz

1 The typical pattern contains a gray scale area, output drive = high. Worst-case pattern is alternating black and white pixels.

2 The typical pattern contains a gray scale area, output drive = high.

3 Specified current and power values with a worst-case pattern (on/off).

4 DATACK load = 10 pF, data load = 5 pF.

5 Drive strength = high.

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