MPC7448 datasheet(41/60 Pages) FREESCALE

41 / 60 page

MPC7448 RISC Microprocessor Hardware Specifications, Rev. 3

Freescale Semiconductor

System Design Information

Power and ground connections must be made to all external VDD, OVDD, and GND pins in the MPC7448.

For backward compatibility with the MPC7447, MPC7445, and MP7441, or for migrating a system

originally designed for one of these devices to the MPC7448, the new power and ground signals (formerly

NC, see Table 11) may be left unconnected if the core frequency is 1 GHz or less. Operation above 1 GHz

requires that these additional power and ground signals be connected, and it is strongly recommended that

all new designs include the additional connections. See also Section 7, “Pinout Listings,” for additional

information.

The MPC7448 provides VDD_SENSE, OVDD_SENSE, and GND_SENSE pins. These pins connect

directly to the power/ground planes in the device package and are intended to allow an external device to

measure the voltage present on the VDD, OVDD and GND planes in the device package. The most common

use for these signals is as a feedback signal to a power supply regulator to allow it to compensate for board

losses and supply the correct voltage at the device. (Note that all voltage parameters are specified at the

pins of the device.) If not used for this purpose, it is recommended that these signals be connected to test

points that can be used in the event that an accurate measurement of the voltage at the device is needed

during system debug. Otherwise, these signals should be connected to the appropriate power/ground

planes on the circuit board or left unconnected.

9.4

Output Buffer DC Impedance

The MPC7448 processor bus drivers are characterized over process, voltage, and temperature. To measure

Z0, an external resistor is connected from the chip pad to OVDD or GND. The value of each resistor is

varied until the pad voltage is OVDD/2. Figure 20 shows the driver impedance measurement.

Figure 20. Driver Impedance Measurement

The output impedance is the average of two components—the resistances of the pull-up and pull-down

devices. When data is held low, SW2 is closed (SW1 is open), and RN is trimmed until the voltage at the

pad equals OVDD/2. RN then becomes the resistance of the pull-down devices. When data is held high,

SW1 is closed (SW2 is open), and RP is trimmed until the voltage at the pad equals OVDD/2. RP then

becomes the resistance of the pull-up devices. RP and RN are designed to be close to each other in value.

Then, Z0 = (RP + RN)/2.

OVDD

OGND

Pad

Data

SW1

SW2

MPC7448 Datasheet(PDF) 41 Page - Freescale Semiconductor, Inc