2

ICS95V157

0501C—11/24/08

Pin Descriptions

This PLL Clock Buffer is designed for a VDD of 2.5V, an AVDD of 2.5V and differential data input and output levels.

ICS95V157 is a zero delay buffer that distributes a single-ended clock input (CLK_INT) to ten differential pair of clock

outputs (CLKT[0:9], CLKC[0:9]) and one single-ended feedback clock output (FB_OUTT). The clock outputs are

controlled by the input clocks (CLK_INT), the feedback clock (FB_INT), the 2.5-V LVCMOS input (PD#) and the analog

power input (AVDD). When input (PD#) is low while power is applied, the receivers are disabled, the PLL is turned off

and the differential clock outputs are tri-stated. When AVDD is grounded, the PLL is turned off and bypassed for test

purposes.

The PLL in the ICS95V157 clock driver uses the input clocks (CLK_INT) and the feedback clock (FB_INT) to provide

high-performance, low-skew, low-jitter, output differential clocks (CLKT [0:9], CLKC [0:9]). ICS95V157 is also able to

track Spread Spectrum Clock (SSC) for reduced EMI.

ICS95V157 is characterized for operation from 0°C to 85°C.

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