3

ICS9248-192

0540F—10/27/05

Power Management

ICS9248-192 Power Management Requirements

Clock Enable Configuration

Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During

power up and power down operations using the PD# pin will not cause clocks of a short or longer pulse than that of

the running clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock

network charging circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also.

Notes.

1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.

2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.

3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.

4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only.

The REF will be stopped independant of these.

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