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LTC2296UP Datasheet(PDF) 2 Page - Linear Technology |
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LTC2296UP Datasheet(HTML) 2 Page - Linear Technology |
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2 / 28 page  LTC2298/LTC2297/LTC2296 2 229876f ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO OVDD = VDD (Notes 1, 2) Supply Voltage (VDD) ................................................. 4V Digital Output Ground Voltage (OGND) ....... –0.3V to 1V Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V) Digital Input Voltage .................... –0.3V to (VDD + 0.3V) Digital Output Voltage ................ –0.3V to (OVDD + 0.3V) Power Dissipation ............................................ 1500mW Operating Temperature Range LTC2298C, LTC2297C, LTC2296C ........... 0°C to 70°C LTC2298I, LTC2297I, LTC2296I ..........–40°C to 85°C Storage Temperature Range ..................–65°C to 125°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER QFN PART* MARKING LTC2298UP LTC2297UP LTC2296UP LTC2298CUP LTC2298IUP LTC2297CUP LTC2297IUP LTC2296CUP LTC2296IUP Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) LTC2298 LTC2297 LTC2296 PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS Resolution ● 14 14 14 Bits (No Missing Codes) Integral Linearity Error Differential Analog Input (Note 5) ● –5 ±1.2 5 –5 ±1.2 5 –5 ±1.2 5 LSB Differential Differential Analog Input ● –1 ±0.5 1 –1 ±0.5 1 –1 ±0.5 1 LSB Linearity Error Offset Error (Note 6) ● –12 ±212 –12 ±212 –12 ±212 mV Gain Error External Reference ● –2.5 ±0.5 2.5 –2.5 ±0.5 2.5 –2.5 ±0.5 2.5 %FS Offset Drift ±10 ±10 ±10 µV/°C Full-Scale Drift Internal Reference ±30 ±30 ±30 ppm/°C External Reference ±15 ±15 ±15 ppm/°C Gain Matching ±0.3 ±0.3 ±0.3 %FS Offset Matching ±2 ±2 ±2mV Transition Noise SENSE = 1V 1 1 1 LSBRMS CO VERTER CHARACTERISTICS TOP VIEW 65 UP PACKAGE 64-LEAD (9mm × 9mm) PLASTIC QFN TJMAX = 125°C, θJA = 20°C/W EXPOSED PAD (PIN 65) IS GND AND MUST BE SOLDERED TO PCB AINA + 1 AINA – 2 REFHA 3 REFHA 4 REFLA 5 REFLA 6 VDD 7 CLKA 8 CLKB 9 VDD 10 REFLB 11 REFLB 12 REFHB 13 REFHB 14 AINB – 15 AINB + 16 48 DA7 47 DA6 46 DA5 45 DA4 44 DA3 43 DA2 42 DA1 41 DA0 40 OFB 39 DB13 38 DB12 37 DB11 36 DB10 35 DB9 34 DB8 33 DB7 |
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