5

ICS93705

0418D—04/28 /05

Timing Requirements

TA = 0 - 70C; Supply Voltage AVDD, VDD = 2.5 V +/-0.2V (unless otherwise stated)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Operating Clock Frequency

1

freqop

66

170

MHz

Input Clock Duty Cycle1

dtin

40

60

%

Clock Stabilization

1

tSTAB

from VDD = 2.5V to 1% target frequency

100

µs

1. Guaranteed by design, not 100% tested in production.

Switching Characteristics

TA = 0 - 70C; Supply Voltage VDD = 2.5 V +/-0.2V (unless otherwise stated)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

66 MHz

120

100 / 125 / 133 / 167 MHz

75

66 MHz

50

110

100 / 125 / 133 / 167 MHz

35

65

Phase Error

1

tpe

with input clock 0-2.5V 0.8ns rise/fall

-150

50

150

ps

Output to output Skew

1

Tskew

with input clock 0-2.5V 0.8ns rise/fall

40

100

ps

Low-to-high level Propagation

Delay Time, Bypass Mode

1

tPLH

CLK_IN to any output, Load = 120W / 12 pF

4

4.5

6

ns

Pulse Skew

1

Tskewp

100

ps

Duty Cycle (differential)

1,3

DC

no loads, 66 MHz to 167 MHz

49

50

51

%

Rise Time, Fall Time

1

tR, tF

Single-ended 20 - 80 %; Load = 120

Ω / 12 pF

450

550

950

ps

1. Guaranteed by design, not 100% tested in production.

2. Refers to transistion on non-inverting period.

3. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies.

This is due to the formula: duty cycle = twH / tC, where the cycle time (tC) decreases as the frequency increases.

ps

ps

Absolute Jitter

1

Cycle to cycle Jitter

1,2

tjabs

tc-c

Recommended Operating Condition

TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Analog/core supply

voltage

VDD, AVDD

2.3

2.5

2.7

V

VIL

-

VDD/2 - 0.5V

V

VIH

VDD/2 + 0.5V

-

V

Input duty cycle

IDC

40

60

%

Input max jitter

ITCYC

500

ps

Input voltage level