List of Figures
82C836 CHIPSet Introduction
Figure 1-1.
SCATsx Basic System Architecture . . . . . . . . . . . . . . . . . . . . . . . 1-2
Pin Assignments
Figure 2-1.
160-Pin PFP Pinout (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Functional Description
Figure 3-1.
Pull-Low Function ----Alternate Implementation . . . . . . . . . . . . . . 3-2
Figure 3-2.
PS Diode for External Real Time Clock Systems . . . . . . . . . . . . . 3-3
Figure 3-3.
Battery Backup Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Clock/Bus Control
Figure 4-1.
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-1
System Interface
Figure 5-1.
MRA Mode Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Figure 5-2.
Encoded RAS Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Figure 5-3.
Example of EMS/Extended Memory . . . . . . . . . . . . . . . . . . . . . . . 5-15
Figure 5-4.
-READYO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
Figure 5-5.
Keyboard Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
Figure 6-1.
Register A----Address 0AH (All Bits Except UIP are Read/Write)
6-4
Figure 6-2.
Register B----Address 0BH (Read Only) . . . . . . . . . . . . . . . . . . . . 6-5
Figure 6-3.
Register C----Address 0CH (Read Only) . . . . . . . . . . . . . . . . . . . . 6-6
Figure 6-4.
Register D----Address 0DH (Read Only) . . . . . . . . . . . . . . . . . . . . 6-7
Figure 6-5.
Update Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-8
Figure 6-6.
Programmable Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
Figure 6-7.
Control Word ----Address 043H . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
Figure 6-8.
Read-Back Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
Figure 6-9.
Status Byte Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
Interrupt Controller
Figure 7-1.
Cascaded Interrupt Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Figure 7-2.
Interrupt Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 7-3
Figure 7-3.
Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
Figure 7-4.
Fixed Priority Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
Figure 7-5.
Specific Rotation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Figure 7-6.
Automatic Rotation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Figure 7-7.
ICW1----Address 020H (0A0H) Write Only . . . . . . . . . . . . . . . . . 7-9
Figure 7-8.
ICW2----Address 021H (0A1H) Write Only . . . . . . . . . . . . . . . . . 7-10
Figure 7-9.
ICW3 Format for INTC1 ----Address 021H Write Only . . . . . . . . . 7-10
Figure 7-10.
ICW3 Format for INTC2 ----Address 0A1H Write Only . . . . . . . . 7-10
Figure 7-11.
ICW4----Address 021H (0A1H) Write Only . . . . . . . . . . . . . . . . . 7-11
Figure 7-12.
OCW----Address 021H (0A1H) Read/Write . . . . . . . . . . . . . . . . . 7-12
Figure 7-13.
OCW2----Address 020H (0A0H) Write Only . . . . . . . . . . . . . . . . 7-13
Figure 7-14.
OCW3----Address 020H (0A0H) Write Only . . . . . . . . . . . . . . . . 7-14
DMA Controller
Figure 8-1.
Cascaded DMA Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Figure 8-2.
Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-10
Figure 8-3.
Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-11
Figure 8-4.
Request Register (Write Operaton) . . . . . . . . . . . . . . . . . . . . . . . . 8-12
82C836 CHIPSet Data Sheet
Contents s
Chips and Technologies, Inc.
P R E L I M I N A R Y
Revision 3.0 ix
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