FXPS7115D4 datasheet(45/72 Pages) NXP

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NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

registers are not guaranteed until the DSP has completed initialization, as specified in Table 105. Reads of the

SNSDATA_x registers and sensor data requests should be prevented during this time.

Location

Bit

Address

4Ch

P_CAL_ZERO_L

P_CAL_ZERO[7:0]

4Dh

P_CAL_ZERO_H

P_CAL_ZERO[15:8]

Reset

Access

R/W

Table 77. P_CAL_ZERO - pressure calibration registers (address 4Ch, 4Dh) bit allocation

The P_CAL_ZERO register value is a signed 16-bit value that is directly added to the internally calibrated

pressure signal value as shown in Equation 6. The equation applies to the values in the 16-bit SNSDATA

registers.

(6)

Note: The pressure calibration registers enable range and resolution options beyond the specified values of the

device. The user must take care to ensure that the value stored in this register does not result in a compressed

output range or a railed output.

7.7.15 DSP_STAT - DSP specific status register (address 60h)

The DSP status register is a read-only register that contains sensor data-specific status information.

Bit

Symbol

reserved

ST_INCMPLT

ST_ACTIVE

CM_ERROR

ST_ERROR

Factory default

Access

Table 78. DSP_STAT - DSP-specific status register (address 60h) bit allocation

Bit

Symbol

Description

ST_INCMPLT

The self-test incomplete bit is set after a device reset and is only cleared when one of the analog or digital self-test

modes is enabled in the ST_CTRL register (ST_CTRL[3] = '1' | ST_CTRL[2] = '1' | | ST_CTRL[1] =

'1' | | ST_CTRL[0] = '1').

0 — An analog or digital self-test has been activated since the last reset.

1 — No analog or digital self-test has been activated since the last reset.

ST_ACTIVE

The self-test active bit is set if any self-test mode is active. The self-test active bit is cleared when no self-test mode is

active.

ST_ACTIVE= ST_CTRL[3] | ST_CTRL[2] | ST_CTRL[1] | ST_CTRL[0]

CM_ERROR

The absolute pressure common mode error status bit is set if the common mode value of the analog front end exceeds

predetermined limits. The CM_ERROR bit is cleared on a read of the DSP_STAT register through any communication

interface or on a data transmission that includes the error in the status field.

ST_ERROR

The self-test error flag is set if an internal self-test fails as described in Section 7.3.1. This bit can only be cleared by a

device reset.

Table 79. DSP_STAT - DSP-specific status register (address 60h) bit description

7.7.16 DEVSTAT_COPY - device status copy register (address 61h)

The device status copy register is a read-only register that contains a copy of the device status information

contained in the DEVSTAT register. See Section 7.7.2.1 "DEVSTAT - device status register (address 01h)" for

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6.2 — 28 June 2023

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