82077AA datasheet(2/62 Pages) INTEL

2 / 62 page

82077AA CHMOS Single-Chip Floppy Disk Controller

CONTENTS

PAGE

10 INTRODUCTION

11 Oscillator

12 Perpendicular Recording Mode

20 MICROPROCESSOR INTERFACE

21 Status Data and Control

Registers

211a Status Register A

(SRA PS2 Mode)

211b Status Register A

(SRA Model 30 Mode)

212a Status Register B

(SRB PS2 Mode)

212b Status Register B

(SRB Model 30 Mode)

213 Digital Output Register

(DOR)

214 Tape Drive Register (TDR)

215 Datarate Select Register

(DRS)

216 Main Status Register

(MSR)

217 FIFO (Data)

218a Digital Input Register

(DIR PC-AT Mode)

218b Digital Input Register

(DIR PS2 Mode)

218c Digital Input Register

(DIR Model 30 Mode)

219a Configuration Control

(CCR PC AT and PS2 Modes)

219b Configuration Control

(CCR Model 30 Mode)

22 RESET

221 Reset Pin (‘‘Hardware’’)

Reset

222 DOR Reset vs DSR Reset

(‘‘Software’’ Reset)

CONTENTS

PAGE

23 DMA Transfers

30 DRIVE INTERFACE

31 Cable Interface

32 Data Separator

321 Jitter Tolerance

322 Locktime (tLOCK)

323 Capture Range

324 Reference Filter

33 Write Precompensation

40 CONTROLLER PHASES

41 Command Phase

42 Execution Phase

421 Non-DMA Mode Transfers

from the FIFO to the Host

422 Non-DMA Mode Transfers

from the Host to the FIFO

423 DMA Mode Transfers from

the FIFO to the Host

424 DMA Mode Transfers from

the Host to the FIFO

425 Data Transfer Termination

43 Result Phase

50 COMMAND SETDESCRIPTIONS

51 Data Transfer Commands

511 Read Data

512 Read Deleted Data

513 Read Track

514 Write Data

515 Write Deleted Data

516 Verify

517 Format Track

5171 Format Fields

518 Scan Commands

82077AA Datasheet(PDF) 2 Page - Intel Corporation

82077AA Datasheet(HTML) 2 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

Datasheet Descarga

Enlace URL