CS5535 datasheet(37/555 Pages) NSC

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Signal Definitions (Continued)

2.2.3.2

Flash Controller Interface

Signal Name

Ball No.

Type

Description

NOR Flash / GPCS Mode

FLASH_CS[3:0]#

C12, A14,

C10, B10

Chip Selects. Combine with FLASH_RE#/WE# strobes to access

external NOR Flash devices or some simple devices such as UART.

CS3# is dedicated to a boot Flash device.

Note:

Ball A14 is the only ball that changes direction from IDE to

Flash (input when in IDE mode, output when in Flash mode).

If this interface is to be switched between IDE and Flash

modes, then ball A14 needs an external pull-up to keep it high

during IDE mode.

FLASH_RE#

B13

Read Enable Strobe. This signal is asserted during READ operations

from the NOR array.

FLASH_WE#

C13

Write Enable Strobe. This signal is asserted during WRITE opera-

tions to the NOR array.

FLASH_ALE

C14

Address Latch Enable. Controls external latch (e.g., 74x373) for

latching the higher address bits in address phase.

FLASH_AD[27:26]/

AD[2:1],

FLASH_AD25/

AD0,

FLASH_AD[24:18]/

AD[9:3]

B11, A12,

A11, B15,

B16, A17,

C17, D16,

D17, E17

Address Bus. During the address phase, address [27:18] is put on

the bus. During the data phase, address [9:0] is put on the bus.

FLASH_AD[17:10]/

IO[7:0]

E16, E15,

D15, B17,

C16, C15,

A15, B14

I/O

Multiplexed Address and I/O Bus. During the address phase, NOR

address [17:10] are placed on these lines. During the data phase, it is

the NOR I/O data bus.

FLASH_IOCHRDY

A13

I/O Channel Ready. When a device is hanging off the bus and wants

to extend its current cycle, it pulls this signal low to insert the wait

state.

NAND Flash Mode

FLASH_CE[3:0]#

C12, A14,

C10, B10

Chip Enables. The signals remain low during entire period of a

NAND cycle.

Note:

Ball A14 is the only ball that changes direction from IDE to

Flash. Needs external pull-up for Flash use.

FLASH_RE#

B13

Read Enable Strobe. This signal is asserted during READ operations

from the NAND array.

FLASH_WE#

C13

Write Enable Strobe. This signal is asserted during WRITE opera-

tions to the NAND array.

FLASH_ALE

C14

Address Latch Enable. Level signal to indicate an address byte is

writing to the NAND Flash device.

FLASH_CLE

A11

Command Latch Enable. Indicates a Command byte is being written

to the device.

FLASH_IO[7:0]

E16, E15,

D15, B17,

C16, C15,

A15, B14

I/O

I/O Bus. I/O Bus for NAND Flash devices. Command, address, and

data are sent on this bus. This bus is actively driven to zero with or

without an LPC_CLK from and after reset.

FLASH_RDY/BUSY#

A13

Ready/Busy#. NAND Flash pulls this signal low to indicate it is busy

with an internal operation. No further action is accepted except read

status.

CS5535 Datasheet(PDF) 37 Page - National Semiconductor (TI)

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