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CS5535 Datasheet(PDF) 126 Page - National Semiconductor (TI) |
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CS5535 Datasheet(HTML) 126 Page - National Semiconductor (TI) |
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126 / 555 page  www.national.com 126 Revision 0.8 UART/IR Controller Functional Description (Continued) 4.11.1 Operational Modes This section describes the operation modes of the UART/IR Controller. Although each mode is unique, certain system resources and features are common. This discussion references several bits in the UART/IR Controller Native register set. Table 4-19 provides the bit map for the UART/IR Controller Native registers for the reader’s convenience. For full bit descriptions, refer to Sec- tion 5.12.2 on page 366. Table 4-19. UART/IR Controller Native Register Bit Map I/O Offset Name 7 654 3210 Bank 0 00h RXD RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0 00h TXD TXD7 TXD6 TXD5 TXD4 TXD3 TXD2 TXD1 TXD0 01h IER (Note 1) RSVD MS_IE LS_IE TXLDL_IE RXHDL_IE IER (Note 2) RSVD TXEMP_IE DMA_IE MS_IE LS_IE TXLDL_IE RXHDL_IE 02h EIR (Note 1) FEN[1:0] RSVD RXFT IPR[1:0] IPF EIR (Note 2) RSVD TXEMP_EV DMA_EV MS_EV LS_EV/ TXHLT_EV TXLDL_EV RXHDL_IE FCR RXFTH[1:0] TXFTH[1:0] RSVD TXSR RXSR FIFO_EN 03h LCR BKSE SBRK STKP EPS PEN STB WLS[1:0] BSR BKSE BSR[6:0] 04h MCR (Note 1) RSVD LOOP ISEN or DCDLP RILP RTS DTR MCR (Note 2) MDSL[2:0] IR_PLS TX_DFR DMA_EN RTS DTR 05h LSR ER_INF TXEMP TXRDY BRK FE PE OE RXDA 06h MSR DCD RI DSR CTS DDCD TERI DDSR DCTS 07h SPR (Note 1) Scratch Data ASCR (Note 2) CTE TXUR RXACT RXWDG RSVD S_OET RSVD RXF_TOUT Bank 1 00h LBGD_L LBGD[7:0] 01h LBGD_H LBGD[15:8] 02h RSVD RSVD 03h LCR BKSE SBRK STKP EPS PEN STB WLS1 WLS0 BSR BKSE BSR[6:0] 04-07h RSVD RSVD Bank 2 00h BGD_L BGD[7:0] 01h BGD_H BGD[15:8] 02h EXCR1 RSVD EDTLBK LOOP DMASWP DMATH DMANF EXT_SL 03h BSR BKSE BSR[6:0] 04h EXCR2 LOCK RSVD PRESL[1:0] RF_SIZ[1:0] TF_SIZ1[1:0] 05h RSVD RSVD 06h TXFLV RSVD TFL[5:0] 07h RXFLV RSVD RFL[5:0] Bank 3 00h MRID MID[3:0] RID[3:0] 01h SH_LCR RSVD SBRK STKP EPS PEN STB WLS1 WLS0 |
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