ST7162 datasheet(8/17 Pages) STMICROELECTRONICS

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Figure 3: 3 Wires Serial Data Transmission Timing

ADDRESS

DATA

D12

TEST 1

D11

TEST 2

D10

TEST 3

AUX. DATA SELECT

REF OUT/3

TX COUNTER ENABLE

RX COUNTER ENABLE

REF. COUNTER ENABLE

AUX. REF. COUNTER ENABLE

MUX SELECT 1

MUX SELECT 2

MUX SELECT 3

MUX SELECT 4

PROGRAMMING THE REGISTER (Figs 3 to 8)

When a Low level is present on the ENABLE in-

put, information on the DATA and AUX DATA in-

puts are used to program the internal registers.

Data are shifted at the rising edge of the clock in-

put. First the 3 address bits of a register are sent,

followed by 12 to 16 data bits, depending on the

lenght of the register. The address is latched at

the 3rd clock impulse following a falling edge at

ENABLE input. This configuration allows to send

various lenght patterns. Moreover, fixed patterns

of 24 or 32 bits can be sent if dummy bits are in-

serted between the address bits and the first data

bit. After the last data bit, a rising edge of the EN-

ABLE input latches the information. When the

VDD supply is switched on, an internal circuit pro-

vides a reset of the control register bits. When the

serial bus is not used, a Low level at clock input

and a HIGH level at ENABLE inputs are applied.

PROGRAMMING THE 3/4 WIRES MODE

When the Auxiliary Data select bit of the control

wires mode at the next pattern. Then one or other

of the 5 registers may be serially loaded by one or

other of the DATA or AUX DATA inputs. When

loading simultaneously 2 registers with different

lenght, dummy bits are inserted between the ad-

dress bits and the data bits of the shorter register

(see fig. 8).

X = DON’T CARE

ST7162

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