CSTS0200MGA06 datasheet(95/153 Pages) STMICROELECTRONICS

95 / 153 page

ST72334J/N, ST72314J/N, ST72124J

95/153

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

DATA REGISTER (DR)

Read/Write

Reset Value: Undefined

Contains the Received or Transmitted data char-

acter, depending on whether it is read from or writ-

ten to.

The Data register performs a double function (read

and write) since it is composed of two registers,

one for transmission (TDR) and one for reception

(RDR).

The TDR register provides the parallel interface

between the internal bus and the output shift reg-

ister (see Figure 1.).

The RDR register provides the parallel interface

between the input shift register and the internal

bus (see Figure 1.).

BAUD RATE REGISTER (BRR)

Read/Write

Reset Value: 00xx xxxx (XXh)

Bit 7:6= SCP[1:0]

First SCI Prescaler

These 2 prescaling bits allow several standard

clock division ranges:

Bit 5:3 = SCT[2:0]

SCI Transmitter rate divisor

These 3 bits, in conjunction with the SCP1 & SCP0

bits define the total division applied to the bus

clock to yield the transmit rate clock in convention-

al Baud Rate Generator mode.

Note: this TR factor is used only when the ETPR

fine tuning factor is equal to 00h; otherwise, TR is

replaced by the ETPR dividing factor.

Bit 2:0 = SCR[2:0]

SCI Receiver rate divisor.

These 3 bits, in conjunction with the SCP1 & SCP0

bits define the total division applied to the bus

clock to yield the receive rate clock in conventional

Baud Rate Generator mode.

Note: this RR factor is used only when the ERPR

fine tuning factor is equal to 00h; otherwise, RR is

replaced by the ERPR dividing factor.

DR7

DR6

DR5

DR4

DR3

DR2

DR1

DR0

SCP1

SCP0

SCT2

SCT1

SCT0

SCR2

SCR1

SCR0

PR Prescaling factor

SCP1

SCP0

TR dividing factor

SCT2

SCT1

SCT0

128

RR dividing factor

SCR2

SCR1

SCR0

128

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