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UPD720100AGM-8EY-A Datasheet(PDF) 21 Page - Renesas Technology Corp |
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UPD720100AGM-8EY-A Datasheet(HTML) 21 Page - Renesas Technology Corp |
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21 / 34 page ![]() Data Sheet S15535EJ3V0DS 19 µPD720100A AC Characteristics (VDD = 3.0 to 3.6 V, TA = 0 to +70°C) PCI Interface Block Parameter Symbol Conditions MIN. MAX. Unit PCI clock cycle time tcyc 30 ns PCI clock pulse, high-level width thigh 11 ns PCI clock pulse, low-level width tlow 11 ns PCI clock, rise slew rate Scr 0.2 VDD to 0.6 VDD 1 4 V/ns PCI clock, fall slew rate Scf 0.2 VDD to 0.6 VDD 1 4 V/ns PCI reset active time (vs. power supply stability) trst 1 ms PCI reset active time (vs. CLK Start) trst-clk 100 µs Output float delay time (vs. RST0 ↓) trst-off 40 ns PCI reset rise slew rate Srr 50 mV/ns PCI bus signal output time (vs. PCLK ↑) tval 2 11 ns PCI point-to-point signal output time (vs. PCLK ↑) tval (ptp) REQ0 2 12 ns Output delay time (vs. PCLK ↑) ton 2 ns Output float delay time (vs. PCLK ↑) toff 28 ns Input setup time (vs. PCLK ↑) tsu 7 ns Point-to-point input setup time (vs. PCLK ↑) tsu (ptp) GNT0 10 ns Input hold time th 0 ns |
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