Motor de Búsqueda de Datasheet de Componentes Electrónicos
  Mexican  ▼
ALLDATASHEET.COM.MX

X  

DSP56367 Datasheet(PDF) 21 Page - Freescale Semiconductor, Inc

No. de pieza DSP56367
Descripción Electrónicos  24-Bit Audio Digital Signal Processor
PDF  100 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricante Electrónico  FREESCALE [Freescale Semiconductor, Inc]
Página de inicio  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

DSP56367 Datasheet(HTML) 21 Page - Freescale Semiconductor, Inc

Back Button DSP56367 Datasheet HTML 17Page - Freescale Semiconductor, Inc DSP56367 Datasheet HTML 18Page - Freescale Semiconductor, Inc DSP56367 Datasheet HTML 19Page - Freescale Semiconductor, Inc DSP56367 Datasheet HTML 20Page - Freescale Semiconductor, Inc DSP56367 Datasheet HTML 21Page - Freescale Semiconductor, Inc DSP56367 Datasheet HTML 22Page - Freescale Semiconductor, Inc DSP56367 Datasheet HTML 23Page - Freescale Semiconductor, Inc DSP56367 Datasheet HTML 24Page - Freescale Semiconductor, Inc DSP56367 Datasheet HTML 25Page - Freescale Semiconductor, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 21 / 100 page
background image
Enhanced Serial Audio Interface_1
DSP56367 Technical Data, Rev. 2.1
Freescale Semiconductor
2-17
SCKR_1
PE0
Input or Output
Input, Output, or
Disconnected
GPIO
Disconnected
Receiver Serial Clock_1—SCKR provides the receiver serial bit clock for the
ESAI. The SCKR operates as a clock input or output used by all the enabled
receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the
synchronous mode (SYN=1).
When this pin is configured as serial flag pin, its direction is determined by the
RCKD bit in the RCCR register. When configured as the output flag OF0, this
pin will reflect the value of the OF0 bit in the SAICR register, and the data in
the OF0 bit will show up at the pin synchronized to the frame sync in normal
mode or the slot in network mode. When configured as the input flag IF0, the
data value at the pin will be stored in the IF0 bit in the SAISR register,
synchronized by the frame sync in normal mode or the slot in network mode.
Port E 0—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input cannot tolerate 3.3V.
SCKT_1
PE3
Input or Output
Input, Output, or
Disconnected
GPIO
Disconnected
Transmitter Serial Clock_1—This signal provides the serial bit rate clock for
the ESAI. SCKT is a clock input or output used by all enabled transmitters and
receivers in synchronous mode, or by all enabled transmitters in
asynchronous mode.
Port E 3—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input cannot tolerate 3.3V.
SDO5_1
SDI0_1
PE6
Output
Input
Input, Output, or
Disconnected
GPIO
Disconnected
Serial Data Output 5_1—When programmed as a transmitter, SDO5 is used
to transmit data from the TX5 serial transmit shift register.
Serial Data Input 0_1—When programmed as a receiver, SDI0 is used to
receive serial data into the RX0 serial receive shift register.
Port E 6—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input cannot tolerate 3.3V.
SDO4_1
SDI1_1
PE7
Output
Input
Input, Output, or
Disconnected
GPIO
Disconnected
Serial Data Output 4_1—When programmed as a transmitter, SDO4 is used
to transmit data from the TX4 serial transmit shift register.
Serial Data Input 1_1—When programmed as a receiver, SDI1 is used to
receive serial data into the RX1 serial receive shift register.
Port E 7—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 3.3V tolerant.
Table 2-12 Enhanced Serial Audio Interface_1 Signals (continued)
Signal
Name
Signal Type
State during
Reset
Signal Description



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100


Datasheet Descarga

Go To PDF Page


Enlace URL



¿ALLDATASHEET es útil para Ud.?  [ DONATE ] 

Todo acerca de Alldatasheet   |   Publicidad   |   Contáctenos   |   Política de Privacidad   |   Enlace a la hoja de datos    |   Intercambio de Enlaces   |   Lista de Fabricantes
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com