WM8721 / WM8721L

Production Data

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PD Rev 4.0 November 2004

18

Right Justified mode is where the LSB is available on the rising edge of BCLK preceding a DACLRC

transition, yet MSB is still transmitted first.

LEFT CHANNEL

RIGHT CHANNEL

DACLRC

BCLK

DACDAT

1/fs

n

3

2

1

n-2 n-1

LSB

MSB

n

3

2

1

n-2 n-1

LSB

MSB

Figure 14 Right Justified Mode

DSP mode is where the left channel MSB is available on either the 1

(selectable by LRP) following a DACLRC transition high. Right channel data immediately follows left

channel data.

LEFT CHANNEL

RIGHT CHANNEL

DACLRC

BCLK

DACDAT

n

3

2

1

n-2 n-1

LSB

MSB

n

3

2

1

n-2 n-1

1 BCLK

Input Word Length (IWL)

Note: Input word length is defined by the IWL register, LRP = 1

1/fs

Figure 15 DSP Mode

In all modes DACLRC must always change on the falling edge of BCLK, refer to Figure 12, Figure

13, Figure 14 and Figure 15.

Operating the digital audio interface in DSP mode allows ease of use for supporting the various

sample rates and word lengths. The only requirement is that all data is transferred within the correct

number of BCLK cycles to suit the chosen word length.

In order for the digital audio interface to offer similar support in the three other modes (Left Justified,

I

more careful consideration.

In Slave mode, DACLRC inputs are not required to have a 50:50 mark-space ratio. BCLK input need

not be continuous. It is however required that there are sufficient BCLK cycles for each DACLRC

transition to clock the chosen data word length. The non-50:50 requirement on the DACLRC is of use

in some situations such as with a USB 12MHz clock. Here simply dividing down a 12MHz clock

within the DSP to generate DACLRC and BCLK will not generate the appropriate DACLRC since it

will no longer change on the falling edge of BCLK. For example, with 12MHz/32k fs mode there are

375 MCLK per DACLRC. In these situations DACLRC can be made non 50:50.