WM8721SEDSSLASHR datasheet(17/37 Pages) WOLFSON

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Production Data

WM8721 / WM8721L

PD Rev 4.0 November 2004

All four of these modes are MSB first and operate with data 16 to 32 bits, except in right

justified mode where 32 bit data is not supported.

The digital audio interface receives the digital audio data for the internal DAC digital filters on the

DACDAT input. DACDAT is the formatted digital audio data stream output to the DAC digital filters

with left and right channels multiplexed together. DACLRC is an alignment clock that controls

whether Left or Right channel data is present on DACDAT. DACDAT and DACLRC are synchronous

with the BCLK signal with each data bit transition signified by a BCLK high to low transition.

DACDAT is always an input. BCLK and DACLRC are either outputs or inputs depending whether the

device is in master or slave mode. Refer to the MASTER/SLAVE OPERATION section

There are four digital audio interface formats accommodated by the WM8721. These are shown in

the figures below. Refer to the Electrical Characteristic section for timing information.

Left Justified mode is where the MSB is available on the first rising edge of BCLK following a

DACLRC transition.

LEFT CHANNEL

RIGHT CHANNEL

DACLRC

BCLK

DACDAT

1/fs

n-2

n-1

LSB

MSB

n-2

n-1

LSB

MSB

Figure 12 Left Justified Mode

2S mode is where the MSB is available on the 2nd rising edge of BCLK following a DACLRC

transition.

LEFT CHANNEL

RIGHT CHANNEL

DACLRC

BCLK

DACDAT

1/fs

n-2

n-1

LSB

MSB

n-2

n-1

LSB

MSB

1 BCLK

Figure 13 I

2S Mode

WM8721SEDS/R Datasheet(PDF) 17 Page - Wolfson Microelectronics plc

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