MP2172C – 2A, SYNCHRONOUS STEP-DOWN SWITCHER

MP2172C Rev.1.0

www.MonolithicPower.com

16

4/22/2019

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For simplification, choose an input capacitor

with an RMS current rating greater than half of

the maximum load current. The input capacitor

can be electrolytic, tantalum, or ceramic. When

using electrolytic or tantalum capacitors, add a

small, high-quality 0.1μF ceramic capacitor as

close to the IC as possible. When using

ceramic capacitors, ensure that they have

enough capacitance to provide a sufficient

charge to prevent excessive voltage ripple at

the input. The input voltage ripple caused by

the capacitance can be estimated with Equation

(7):

LOAD

OUT

OUT

IN

IN

SIN

IV

V

V1

fC1

V

V







 







(7)

Selecting the Output Capacitor

The output capacitor (C2) stabilizes the DC

output voltage. Low ESR ceramic capacitors

are recommended to limit the output voltage

ripple. Estimate the output voltage ripple with

Equation (8):

OUT

OUT

OUT

ESR

S1

IN

S

VV

1

V1

R

fL

V

8 f

C2







 









 

 

(8)

Where L1 is the inductor value, and RESR is the

equivalent series resistance (ESR) value of the

output capacitor.

When

using

ceramic

capacitors,

the

capacitance dominates the impedance at the

switching frequency and causes most of the

output voltage ripple. For simplification, the

output voltage ripple can be estimated with

Equation (9):

OUT

OUT

OUT

2

S1

IN

VV

∆V1

8f

L

C2

V



 



 



(9)

For tantalum or electrolytic capacitors, the ESR

dominates the impedance at the switching

frequency. For simplification, the output ripple

can be approximated with Equation (10):

OUT

OUT

OUT

ESR

IN

S1

VV

∆V1

R

fL

V



 









(10)

The characteristics of the output capacitor also

affect the stability of the regulation system.

PCB Layout Guidelines

Efficient PCB layout is critical for stable

operation. For the high-frequency switching

converter, improper layout design can result in

poor line or load regulation and stability issues.

For best results, refer to Figure 10 and follow

the guidelines below:

1. Place the high-current paths (GND, VIN,

and SW) very close to the device with short,

direct, and wide traces.

2. Place the input capacitor as close to VIN

and GND as possible.

3. Place the external feedback resistors next

to FB.

4. Keep SW short and away from the feedback

network.

5. Keep the VOUT sense line need as short as

possible and away from the power inductor,

especially the surrounding inductor.

Figure 10: Recommended Layout for the

MP2172C