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ES9018 Datasheet(PDF) 13 Page - ESS Technology,Inc

No. de pieza ES9018
Descripción Electrónicos  Reference 32-bit Audio DAC
PDF  54 Pages
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Fabricante Electrónico  ESS [ESS Technology,Inc]
Página de inicio  http://www.esstech.com
Logo ESS - ESS Technology,Inc

ES9018 Datasheet(HTML) 13 Page - ESS Technology,Inc

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ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM
COM
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ES9018S Product Datasheet
Data Clock
DATA_CLOCK must be 64 x Fs for SERIAL, Fs for DSD modes, and is not required for SPDIF mode. This pin should be pulled low if not used.
Built-in Digital Filters
There are numerous applications for a stereo DAC so for added flexibility; two digital filter settings are possible, sharp roll-off and a slow roll-off for
PCM mode. For DSD mode, there are four available filters with cutoffs at 47kHz, 50kHz, 60kHz, and 70kHz.
Sample Rate Calculation
The DPLL number can be read back from the SABRE32 Reference, allowing for calculation of the sample rate. The sample rate can be calculated
using: Fin = (DPLL_NUM x Fcrystal) / 232. Fin must be divided by 64 for I2S data.
DAC-bar Phase
Each DAC-bar phase can be configured to be in phase with DAC. This allows for the outputs of the DAC to be summed to drive an amplifier.
DPLL Lock Reset
The DPLL can be forced to relock, which is useful when the sample rate has been changed. This can be done by setting Register 17
<dpll_lock_rst_reg> high to force the reset, and then low to resume normal operation.
DPLL Frequency Phase Flip
The DPLL can be set to lock to either the rising or falling edge of the clock. This can be set using Register 17 <fin_phase_flip>.
PCM Audio Interface Formats
Several interface formats are provided so that direct connection to common audio processors is possible. The available formats and their
accompanying diagrams are listed in the following table. The audio interface format can be set by programming the registers.
Format
Description
Figure
0
MSB First, Left Justified, up to 32-bit data
1A
1
I2S, up to 32-bit data
3A
2
MSB First, Right Justified, 32-bit data
2A
3
MSB First, Right Justified, 24-bit data
2B
4
MSB First, Right Justified, 20-bit data
2C
5
MSB First, Right Justified, 16-bit data
2D
6
DSD Normal Mode
4A
7
DSD Phase Mode
4B
Table 8 - PCM Audio Interface Formats



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