VSC8541XMV-02 datasheet(66/101 Pages) MICROCHIP

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Registers

VMDS-10513 VSC8541-02 Datasheet Revision 4.1

4.4.13

Ring Resiliency Control

The following table shows the register settings for the ring resiliency controls at address 30E2.

4.5

General Purpose Registers

Accessing the general purpose register space is similar to accessing the extended page registers. Set

To restore main register page access, write 0x0000 to register 31. All general purpose register bits are

super-sticky.

RR switchover complete interrupt status

Self-clearing bit.

1: Interrupt pending.

EEE link fail interrupt status

Self-clearing bit.

1: Interrupt pending.

EEE Rx TQ timer interrupt status

Self-clearing bit.

1: Interrupt pending.

EEE wait quiet/Rx TS timer interrupt status

Self-clearing bit.

1: Interrupt pending.

EEE wake error interrupt mask

Self-clearing bit.

1: Interrupt pending.

Table 70 •

Ring Resiliency, Address 30E2 (0x1E)

Bit

Name

Access Description

Default

Ring resiliency startup enable

(master TR enable)

R/W

Sticky.

Advertise ring resiliency

R/W

Sticky.

LP ring resiliency advertisement

Force ring resiliency enable

(override autoneg)

R/W

Sticky.

11:6

Reserved

Reserved.

5:4

Ring resiliency status

Ring resiliency status.

00: Timing slave1

10: Timing slave becoming master

11: Timing master1

01: Timing master becoming slave

Reflects autoneg master/slave at initial link-up.

3:1

Reserved

Reserved.

Start switchover (only when not in

progress)

R/W

Self clearing.

1: Initiate timing Master/Slave switchover.

Table 71 •

General Purpose Registers Space

Address

Name

0G–12G

Reserved

13G

CLKOUT Control

Table 69 •

Extended Interrupt Status, Address 29E2 (0x1D) (continued)

Bit

Name

Access Description

Default

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