WM8728

Production Data

w

PD Rev 4.2 April 2004

15

DSP LATE MODE

In DSP late mode, the first bit is sampled on the BCKIN rising edge, which detects a low to high

transition on LRCIN. No BCKIN edges are allowed between the data words. The word order is

DIN left, DIN right.

LRCIN

BCKIN

DIN

Input Word Length (IWL)

1/fs

LEFT CHANNEL

n

2

1

n-1

LSB

MSB

n

2

1

n-1

RIGHT CHANNEL

NO VALID DATA

1

Figure 10 DSP Late Mode Timing Diagram

AUDIO DATA SAMPLING RATES

The master clock for WM8728 can range from 128fs to 768fs, where fs is the audio sampling

frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The master clock is used

to operate the digital filters and the noise shaping circuits.

The WM8728 has a master clock detection circuit that automatically determines the relationship

between the master clock frequency and the sampling rate (to within +/- 32 system clocks). If

there is a greater than 32 clocks error, the interface shuts down the DAC and mutes the output.

The master clock should be synchronised with LRCIN, although the WM8728 is tolerant of phase

differences or jitter on this clock. See Table 1

MASTER CLOCK FREQUENCY (MHZ) (MCLK)

SAMPLING

RATE

(LRCIN)

128fs

192fs

256fs

384fs

512fs

768fs

32kHz

4.096

6.144

8.192

12.288

16.384

24.576

44.1kHz

5.6448

8.467

11.2896

16.9340

22.5792

33.8688

48kHz

6.114

9.216

12.288

18.432

24.576

36.864

96kHz

12.288

18.432

24.576

36.864

Unavailable

Unavailable

192kHz

24.576

36.864

Unavailable

Unavailable

Unavailable

Unavailable

Table 1 Typical Relationships Between Master Clock Frequency and Sampling Rate