WM8772SEDSSLASHV datasheet(60/73 Pages) WOLFSON

60 / 73 page

WM8772EFT – 32 LEAD TQFP

Production Data

PD Rev 4.2 October 2005

DAC DIGITAL AUDIO INTERFACE CONTROL REGISTER

Interface format is selected via the DACFMT[1:0] register bits:

BIT

LABEL

DEFAULT

DESCRIPTION

0000011

Interface Control

1:0

DACFMT

[1:0]

Interface Format Select:

00 : Right justified mode

01: Left justified mode

10: I

2S mode

11: DSP mode A or B

In left justified, right justified or I

2S modes, the DACLRP register bit controls the polarity of DACLRC.

If this bit is set high, the expected polarity of DACLRC will be the opposite of that shown Figure 23,

Figure 24 and Figure 25. Note that if this feature is used as a means of swapping the left and right

channels, a 1 sample phase difference will be introduced. In DSP modes, the DACLRP register bit is

used to select between mode A and mode B.

BIT

LABEL

DEFAULT

DESCRIPTION

In Left/Right/I

2S Modes:

DACLRC Polarity (normal)

0 : Normal DACLRC polarity

1: Inverted DACLRC polarity

0000011

Interface Control

DACLRP

In DSP Mode:

0 : DSP mode A

1: DSP mode B

By default, DACLRC and DIN1/2/3 are sampled on the rising edge of DACBCLK and should ideally

change on the falling edge. Data sources that change DACLRC and DIN1/2/3 on the rising edge of

DACBCLK can be supported by setting the BCP register bit. Setting DACBCP to 1 inverts the

polarity of DACBCLK to the inverse of that shown in Figure 47 to Figure 57.

BIT

LABEL

DEFAULT

DESCRIPTION

0000011

Interface Control

DACBCP

DACBCLK Polarity (DSP Modes)

0 : Normal BCLK polarity

1: Inverted BCLK polarity

The DACIWL[1:0] bits are used to control the input word length.

BIT

LABEL

DEFAULT

DESCRIPTION

0000011

Interface Control

5:4

DACIWL

[1:0]

Input Word Length:

00 : 16 bit data

01: 20 bit data

10: 24 bit data

11: 32 bit data

Note: If 32-bit mode is selected in right justified mode, the WM8772EFT defaults to 24 bits.

In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the

DAC is programmed to receive 16 or 20 bit data, the WM8772EFT pads the unused LSBs with zeros.

If the DAC is programmed into 32 bit mode, the 8 LSBs are ignored.

Note: In 24 bit I

2S mode, any width of 24 bits or less is supported provided that DACLRC is high for a

minimum of 24 BCLKs and low for a minimum of 24 BCLKs.

A number of options are available to control how data from the Digital Audio Interface is applied to

the DAC channels.

WM8772SEDS/V Datasheet(PDF) 60 Page - Wolfson Microelectronics plc

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