TMS320C6421 datasheet(7/59 Pages) TI

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2.3 Memory Map Summary

TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346A – JANUARY 2007 – REVISED MARCH 2007

Table 2-5 shows the memory map address ranges of the device. Table 2-6 depicts the expanded map of

the Configuration Space (0x0180 0000 through 0x0FFF FFFF). The device has multiple on-chip memories

associated with its two processors and various subsystems. To help simplify software development a

unified memory map is used where possible to maintain a consistent view of device resources across all

bus masters.

Table 2-5. Memory Map Summary

START

END

SIZE

C64x+

EDMA PERIPHERAL

ADDRESS

(Bytes)

MEMORY MAP

0x0000 0000

0x000F FFFF

Reserved

0x0010 0000

0x0010 FFFF

64K

Boot ROM

0x0011 0000

0x007F FFFF

7M-64K

Reserved

0x0080 0000

0x0080 FFFF

64K

Reserved

0x0081 0000

0x0081 FFFF

64K

L2 RAM/Cache(1)

0x0082 0000

0x00E0 7FFF

6048K

Reserved

0x00E0 8000

0x00E0 BFFF

16K

Reserved

0x00E0 C000

0x00E0 FFFF

16K

L1P RAM/Cache(2)

0x00E1 0000

0x00F0 3FFF

976K

Reserved

0x00F0 4000

0x00F0 FFFF

48K

Reserved

0x00F1 0000

0x00F1 3FFF

16K

Reserved

0x00F1 4000

0x00F1 7FFF

16K

L1D RAM/Cache(2)

0x00F1 8000

0x017F FFFF

9120K

Reserved

0x0180 0000

0x01BF FFFF

CFG Space

0x01C0 0000

0x01FF FFFF

CFG Bus Peripherals

0x0200 0000

0x100F FFFF

225M

Reserved

0x1010 0000

0x1010 FFFF

64K

Boot ROM

Reserved

0x1011 0000

0x107F FFFF

7M-48K

Reserved

0x1080 0000

0x1080 FFFF

64K

Reserved

0x1081 0000

0x1081 FFFF

64K

L2 RAM/Cache(1)

0x1082 0000

0x10E0 7FFF

6048K

Reserved

0x10E0 8000

0x10E0 BFFF

16K

Reserved

0x10E0 C000

0x10E0 FFFF

16K

L1P RAM/Cache(2)

0x10E1 0000

0x10F0 FFFF

Reserved

0x10F1 0000

0x10F1 3FFF

16K

Reserved

0x10F1 4000

0x10F1 7FFF

16K

L1D RAM/Cache(2)

0x10F1 8000

0x1FFF FFFF

241M-96K

Reserved

0x2000 0000

0x2000 7FFF

32K

DDR2 Control Regs

0x2000 8000

0x41FF FFFF

544M-32K

Reserved

0x4200 0000

0x42FF FFFF

16M

EMIFA Data (CS2)(3)

0x4300 0000

0x43FF FFFF

16M

Reserved

0x4400 0000

0x44FF FFFF

16M

EMIFA Data (CS3)(3)

0x4500 0000

0x45FF FFFF

16M

Reserved

0x4600 0000

0x46FF FFFF

16M

EMIFA Data (CS4)(3)

0x4700 0000

0x47FF FFFF

16M

Reserved

0x4800 0000

0x48FF FFFF

16M

EMIFA Data (CS5)(3)

0x4900 0000

0x4BFF FFFF

48M

Reserved

0x4C00 0000

0x4FFF FFFF

64M

VLYNQ (Remote Data)

0x5000 0000

0x7FFF FFFF

768M

Reserved

0x8000 0000

0x8FFF FFFF

256M

DDR2 Memory Controller

0x9000 0000

0xFFFF FFFF

1792M

Reserved

(1)

On the C6421, L2 RAM/Cache defaults to all RAM (L2CFG.L2MODE = 0h)

(2)

To intialize L1P and L1D RAM/Cache to a valid cache setting, the user must follow the sequence outlined in , Device Initialization

Sequence After Reset.

(3)

The EMIFA CS0 and CS1 are not functionally supported on the C6421 device, and therefore, are not pinned out.

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