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MSP430F14X Datasheet(PDF) 56 Page - Texas Instruments |
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MSP430F14X Datasheet(HTML) 56 Page - Texas Instruments |
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56 / 83 page ![]() P5.3/UCLK1 P5IN.3 Pad Logic EN D P5OUT.3 P5DIR.3 P5SEL.3 0 1 0 1 DCM_SIMO SYNC MM STE STC UCLK1 From USART1 UCLK1 To USART1 0: Input 1: Output P5.2/SOMI1 P5IN.2 Pad Logic EN D P5OUT.2 P5DIR.2 P5SEL.2 0 1 0 1 DCM_SOMI SYNC MM STE STC SO(MI)1 From USART1 (SO)MI1 To USART1 0: Input 1: Output 56 MSP430F149, MSP430F148, MSP430F147 MSP430F1491, MSP430F1481, MSP430F1471 MSP430F135, MSP430F133 SLAS272H – JULY 2000 – REVISED MAY 2018 www.ti.com Submit Documentation Feedback Product Folder Links: MSP430F149 MSP430F148 MSP430F147 MSP430F1491 MSP430F1481 MSP430F1471 MSP430F135 MSP430F133 Detailed Description Copyright © 2000–2018, Texas Instruments Incorporated Figure 6-22. Port P5 (P5.2) Diagram NOTE: UART mode: The UART clock can only be an input. If UART mode and UART function are selected, P5.3/UCLK1 is always an input. SPI slave mode: The clock applied to UCLK1 is used to shift data in and out. SPI master mode: The clock to shift data in and out is supplied to connected devices on pin P5.3/UCLK1 (in slave mode). Figure 6-23. Port P5 (P5.3) Diagram |
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